Double integration analog to digital converting device

An analog to digital converting device, comprising:

• first integrating means including a first operational amplifier connected to receive a first analog signal which is to be converted into a digital signal, a first integrating capacitor connected between an input terminal and an output terminal of said first operational amplifier, and a first reset switch connected in parallel to said first integrating capacitor;
• a second integrating means including a second operational amplifier connected to receive a second analog signal which is to be converted into a second digital signal, a second integrating capacitor connected between an input terminal and an output terminal of said second operational amplifier, and a second reset switch connected in parallel to said second integrating capacitor;
• a first comparator connected to an output terminal of said first integrating means;
• a second comparator connected to an output terminal of said second integrating means;
• integration starting means for starting an integrating operation of said first and said second integrating means, said integration starting means including a first integrating switch having an enabling state and a disabling state for controlling the input of said first analog signal to said first integrating means and a second integrating switch having an enabling state and a disabling state for controlling the input of said second analog signal to said second integrating means, said first and said second integrating switches being enabled at the same time to start the integrating operation of said first and said second integrating means;
• inverse integration starting means for starting an inverse integrating operation of said first and said second integrating means, said inverse integration starting means including a first inverse integrating switch having an enabling state and a disabling state for controlling an output from said first integrating means and a second inverse integrating switch having an enabling state and a disabling state for controlling an output from said second integrating means, said first and said second inverse integrating switches being enabled at the same time to start the inverse integrating operation of said first and said second integrating means;
• controlling means for activating said first and said second reset switches of the respective first and second integrating means, said integration starting means and said inverse integration starting means in this order with said controlling means placing said first and said second integrating switches in the disabling state at the same time as placing said first and said second inverse integrating switches in the enabling state;
• first limiting means connected in parallel to said first integrating capacitor for limiting an amount of charge to be accumulated in said first integrating capacitor by an inverse integrating operation to below a predetermined level;
• and
• second limiting means connected in parallel to said second integrating capacitor for limiting an amount of charge to be accumulated in said second integrating capacitor by an inverse integrating operation to below a predetermined level.