US 4,771,013 A · Process of making a double heterojunction 3-D I.sup.2 L bipolar transistor with a Si/Ge superlattice

Abstract

A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, and structure formed thereby includes a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100> crystal orientation, which is etched and with three dimensional transistors formed in it. Passivation for and contacts to said circuits are established, and the circuits are interconnected. The high voltage and high power transistors include transistors of an H-bridge circuit, including at least one set of cascode double heterojunction transistors, the analog transistors include a bipolar transistor, and the digital transistors include transistors of a I.sup.2 L circuit. One method for constructing the wafer is by sequentially epitaxially depositing each strata in an UHV silicon-based MBE apparatus. Another method is by constructing guest and host wafers, each containing respective portions of the strata, and fusing said guest and host wafers together.

Claims38

Dependent claims

A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, comprising:

(a) providing a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100>
crystal orientation including:
i. an n type semimetal layer;
ii. a first n.sup.+ type silicon region;
iii. a first n type silicon region;
iv. a first Ge.sub.x Si.sub.1-x /Si superlattice;
v. a second n.sup.+ type silicon region;
vi. an n type semimetal boundary;
vii. a monocrystalline conductor;
viii. n type semimetal boundary;
ix. a third n.sup.+ type silicon region;
x. a second n type silicon region;
xi. a second Ge.sub.x Si.sub.1-x Si/supperlattice;
xii. a fourth n.sup.+ type region;
xiii. an n type semimetal boundary;
(b) etching said wafer to expose predetermined strata of said wafer;
(c) forming at least one set of cascode double heterojunction transistors in said epitaxial strata;
(d) establishing passivation for and contacts to said circuits;
(e) and interconnecting the circuits.

16 more elements

A three dimensional, bipolar wafer process for integrating high voltage, high power, analog, and digital circuitry, comprising:

(a) providing a wafer of non-compensated epitaxial strata on a heavily donor doped monocrystalline silicon substrate of <100>
crystal orientation including:
i. an n-semimetal layer of thickness between about 0.5 to 1.0 microns;
ii. a first n.sup.+ type silicon region having a thickness of between about one to 15 microns with a donor concentration of about 5.times.10.sup.17 atoms/cm.sup.3 ;
iii. a first n type silicon region of thickness greater than 10 microns with a donor doping concentrations between about 1.times.10.sup.14 atom/cm.sup.3 to 5.times.10.sup.15 atom/cm.sup.3 ;
iv. a first Ge.sub.x Si.sub.1-x /Si superlattice of thickness of less than 1 micron and having an acceptor doping concentration of at least 10.sup.20 atoms/cm.sup.3 ;
v. a second n.sup.+ type silicon region having a thickness of between about one to 15 microns with a donor concentration of about 5.times.10.sup.17 atoms/cm.sup.3 ;
vi. an n type semimetal boundary of thickness between about 0.5 to 1.0 microns;
vii. a monocrystalline conductor of monocrystalline NiSi.sub.2 ;
viii. n type semimetal boundary of thickness between about 0.5 to 1.0 microns;
ix. a third n.sup.+ type silicon region having a thickness of between about one to 15 microns with a donor concentration of about 5.times.10.sup.17 atoms/cm.sup.3 ;
x. a second n type silicon region of thickness greater than 10 microns with a donor doping concentrations between about 1.times.10.sup.14 atom/cm.sup.3 to 5.times.10.sup.15 atom/cm.sup.3 ;
xi. a second Ge.sub.x Si.sub.1-x /Si superlattice of thickness of less than 1 micron and having an acceptor doping concentration of at least 10.sup.20 atoms/cm.sup.3 ;
xii. a fourth n.sup.+ type region having a thickness of between about one to 15 microns with a donor concentration of about 5.times.10.sup.17 atoms/cm.sup.3 ;
xiii. an n type semimetal boundary of thickness between about 0.5 to 1.0 microns;
(b) etching said wafer to expose predetermined strata of said wafer;
(c) forming an H-bridge circuit in said epitaxial strata including at least one set of double heterojunciton transistors by forming a cascode source NPN transistor with said first n.sup.+ type silicon region as a collector boundary, said first n type silicon region as a collector, said first Ge.sub.x Si.sub.1-x /Si superlattice as a base, and said second n.sup.+ type silicon region as an emitter, and forming a cascode sink NPN transistor with said third n.sup.+ type silicon region as a collector boundary, said second n type silicon region as a collector, said second Ge.sub.x Si.sub.1-x /Si superlattice as a base, and said fourth n.sup.+ type region as an emitter.
(d) forming a bipolar transistor in said epitaxial strata, including forming a p type semimetal on said fourth n.sup.+ type silicon layer, with said p type semimetal as an emitter, said fourth n.sup.+ layer as a base, and said second Ge.sub.x Si.sub.1-x /Si superlattice as a collector, and forming an I.sup.2 L circuit in said epitaxial strata including at least two NPN transistors each with said third n.sup.+ type silicon region as an emitter boundary, said second n type silicon region as an emitter, said second Ge.sub.x Si.sub.1-x /Si superlattice as a base, and said fourth n.sup.+ type region as an collector.
(e) establishing passivation for and contacts to said circuits;
(f) and interconnecting the circuits.

17 more elements

Dependencies are inferred from the claim text.

Process of making a double heterojunction 3-D I.sup.2 L bipolar transistor with a Si/Ge superlattice

Life of this patent

Process of making a double heterojunction 3-D I.sup.2 L bipolar transistor with a Si/Ge superlattice

Life of this patent

Abstract

Claims38