Method of manufacturing a field effect transistor device having a multilayer gate electrode
AssigneeKabushiki Kaisha Toshiba
InventorTetsuo Ishii
Life of this patent
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Abstract
This Schottky barrier gate field effect transistor has N.sup.+ -type source and drain regions formed in the surface area of a GaAs semi-insulation substrate, a channel region formed between the source and drain regions, and a gate electrode formed on this channel region. Particularly, in this Schottky barrier gate field effect transistor, the gate electrode has a first metal portion, which is preferably in Schottky contact with the channel region, and a second metal portion, which stably affixes to the first metal portion. The first and second metal portions are fixed to an insulative portion formed on the channel region.
Claims7
A method of manufacturing a field effect transistor device comprising:
- a first step of forming an active region in a surface of a semiconductor substrate;
- a second step of forming a multilayer gate electrode on and in Schottky contact with said active region;
- a third step of forming a first insulative spacer on said active region and in fixed contact with a side surface of said gate electrode;
- a fourth step of uniformly depositing an insulative layer on said active region, gate electrode and first insulative spacer and anisotropically etching said insulative layer until the active region is exposed to provide portions of said insulative layer in fixed contact with an opposite side surface of said gate electrode and on side surfaces of said first insulative spacer to form second and third insulative spacers, respectively;
- and
- a fifth step of forming source and drain regions in said active region by using as a mask said first, second and third spacers and gate electrode with said source and drain regions having a higher carrier concentration than said active region, said source region being spaced from said gate electrode by a first distance substantially equal to the thickness of said second insulative spacer, and said drain region being spaced from said gate electrode by a second distance substantially equal to the sum of the thickness of said first and third spacers.
Dependencies are inferred from the claim text.