Frame decoding

A method of frame decoding, in a multiplexer-demultiplexer system for digital signal transmission in which a series data flow (DS) has a frame structure including an item of periodically occurring synchronizing information which characterizes the start of each frame, comprising the steps of

• synchronizing a frame recognition circuit (SZ) to the periodically occurring item of synchronizing information, in which one single synchronizing bit (SB) is used as said synchronizing information,
• following a predetermined number of correctly recognized items of synchronizing information, coupling a frame generator (AZ) to said frame recognition circuit,
• determining in each successive frame coincidence between a synchronizing signal (SS) which is emitted from the frame generator and the item of synchronizing information, to establish that synchronous coincidence is maintained,
• increasing the count of a weighting counter (GZ) by a predetermined quantity, periodically, in the case of synchronous coincidence, up to a maximum count, and reducing the count of said weighting counter by a predetermined quantity, periodically, in the case of non-coincidence, down to a minimum count,
• decoupling said frame generator from said frame recognition circuit, when the maximum count of the weighting counter (GZ) is reached,
• checking said data flow for a further item of synchronizing information in each frame and gating out each item of synchronizing information contained in the frame generator,
• performing resynchronization of the frame generator to the frame recognition circuit only when the count of the weighting counter (GZ) has reached its minimum count and the frame recognition circuit has correctly recognized a predetermined number of items of synchronizing information,
• supplying said data flow (DS) to the input of a shift register (SR),
• tapping an output (A) of said shift register (SR) which occupies a specific bit position within the frame,
• logic-linking data at the said tappped output via an AND-gate (AD2) with a bit of the data flow (DS) which occupies the same bit position,
• supplying the logic-link result to an input (E) of the shift register (SR), whereby, after a plurality of frame lengths only the synchronizing bit (SB) passes through the shift register (SR),
• said search counter (SZ), having a maximum count corresponding to the number of bits in the frame,
• resetting said search counter by supplying thereto logic ones emitted from the output A of the shift register (SR) whereby, when only one bit corresponding to the synchronizing bits (SB) is set at logic "1" in the shift register (SR), a pulse which is synchronous to said synchronizing bit (SB) is emitted from the carry output (TC) of the search counter (SZ).