Programming arrangement for a non-volatile memory for a timepiece

In a timepiece having an electrically alterable non-volatile memory, said timepiece including an oscillator, a multistage frequency divider the division rate of which is adjustable by alteration of a number k of pulses furnished by a stage thereof, the number k being representative of the frequency difference between the oscillator frequency and a standard frequency and appearing in a binary form recorded in the non-volatile memory in order to modify the contents of certain predetermined stages of the divider at regular intervals, a stepping motor receiving driving pulses from the divider to display time in an analog manner and a receptacle adapted to accommodate an energy cell, a programming arrangement for said non-volatile memory, said programming arrangement comprising;

• first means controlled by the end of a driving pulse so as to introduce into said predetermined divider stages a binary state corresponding to said number k and second means for blocking the contents of said stages as soon as said binary state has been attained and thereafter recording said contents in said non-volatile memory, said first means being located externally to the timepiece and electrically coupled thereto by means of a connector plugged into the energy cell receptacle by its two terminals, said first means comprising an energy source for energizing the timepiece by a low level voltage or a high level voltage, a memory-counter into which may be introduced the number k, a time base the frequency of which is coarsely adjusted to the frequency of the timepiece oscillator, a detector for driving pulses the output edges of which coincide with the zero resetting of said predetermined divider stages, the output edge of one of said driving pulses defining the beginning of a period TD the duration of which is defined by the time necessary to introduce into said predetermined stages the binary state corresponding to the number k contained in the memory-counter, a switch for switching the energy source over to the high level voltage as soon as the end of said period TD is reached and a delay circuit for maintaining said voltage at its high level over a predetermined period Ti, and wherein the second means are incorporated into the timepiece and include a voltage level detector which when said voltage has attained a predetermined value situated between said low and high level voltages blocks the contents of said predetermined divider stages at the binary value they have attained at the end of said period TD and records said contents in said non-volatile memory during said predetermined period Ti.