US 4,761,384 A · Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing

Abstract

A method for the manufacture of LSI complementary MOS field effect transistor circuits to increase the latch-up hardness of the n-channel and p-channel field effect transistors while retaining good transistor properties by incorporating a further epitaxial layer and highly doped implantation regions into a lower epitaxial layer from which the wells are generated by out-diffusion into the upper epitaxial layer. In addition to achieving optimum transistor properties, the reduced lateral diffusion provided enables a lower n.sup.+ /p.sup.+ spacing, and thus achieves a higher packing density with improved latch-up hardness.

Claims16

Dependent claims

A method for the manufacture or complementary MOS field effect transistor circuits which comprises:

providing an n.sup.+ -doped or p.sup.+ -doped silicon substrate having a first n.sup.- -doped or p.sup.- -doped epitaxial layer, respectively, thereon,
implanting a comparatively high dosage of dopant into said first epitaxial layer to form highly doped buried layers,
depositing a second epitaxial layer over said highly doped layer, and
generating n-doped or p-doped wells by diffusion out from said highly doped epitaxial layer into said second epitaxial layer.

1 more element

A method for the manufacture of complementary MOS field effect transistors which comprises:

(a) providing an n.sup.+ -doped silicon substrate having a first n.sup.- -doped epitaxial layer thereon,
(b) generating an insulating double layer of SiO.sub.2 and silicon nitrate on said n.sup.+ -doped silicon substrate,
(c) applying a photoresist mask over the region in which an n-well is to be generated,
(d) implanting a relatively high concentration of boron ions in the p-well area to be generated to form a highly doped buried layer using said photoresist mask and the silicon nitride as masking,
(e) oxidizing the surface of said p-well area for masking said area,
(f) removing the nitride layer from said n-well region,
(g) implanting a relatively large dosage of phosphorous or arsenic ions in said n-well region as to form a highly doped buried layer,
(h) etching off said masking,
(i) depositing a second epitaxial layer over the resulting surface,
(j) forming a surface-wide insulating oxide layer over the resulting surface,
(k) diffusing out the ions from said buried layers into the respective wells,
(l) masking the entire active transistor regions with a silicon nitride layer,
(m) masking the n-well regions with a photoresist layer,
(n) implanting the n-channel field oxide transistors in the region of the p-well,
(o) removing said photoresist layer,
(p) locally oxidizing the field oxide region as to form an oxide layer using said silicon nitride layer as a masking,
(q) stripping off the silicon nitride masking,
(r) thermally oxidizing the entire remaining surface,
(s) etching said oxide layer,
(t) generating a gate oxide region to a predetermined thickness,
(u) carrying out channel doping with boron ions in two steps including a deep implantation in the first step and a flat implantation in the second step, and
(v) applying gate electrodes to the gate regions and generating the source/drain regions, the insulation layer, the contact holes, and the metalitation in a known manner.

19 more elements

Dependencies are inferred from the claim text.

Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing

Life of this patent

Forming retrograde twin wells by outdiffusion of impurity ions in epitaxial layer followed by CMOS device processing

Life of this patent

Abstract

Claims16