Data processor capable of executing instructions under prediction
AssigneesHitachi, Ltd., Hitachi Microcomputer Eng.
InventorsYooichi Shintani, Tohru Shonai, Eiki Kamada, Shigeo Takeuchi
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Abstract
A buffer or a plurality of buffers are provided each for holding a write address and an address specifying a write position which are obtained as a result of an execution based on a predicted result. The execution of the instruction is continued up to the operation stage regadless of whether or not the instruction is being executed in the predicted state, the data and the write address are held in the buffer written. The data in the buffer is canceled if the prediction is found to be wrong when the predicted state is completed, and the data is utilized if the prediction is found to be correct.
Claims10
A data processor comprising:
- processing means for decoding a plurality of instructions, for executing a succeeding instruction in concurrence with a preceding instruction previously decoded, said succeeding instruction being executed by prediction that a predetermined execution result will be obtained for said preceding instruction when validity of an execution result of said succeeding instruction is dependent on a true execution result of said preceding instruction, and for outputting an execution result data of said succeeding instruction, a write address representing a location to write said execution result data, and a flag signal indicating that said execution result data is provided for an instruction which was executed based on said prediction, said processing means including means for providing a validity signal for indicating whether or not said true execution result of said preceding instruction coincides with said predetermined execution result;
- means connected to said processing means for storing said execution result data, said write address, and said flag signal obtained as a result of execution of said succeeding instruction;
- and
- control means responsive to said validity signal and including means for transferring said execution result data and said write address from said sotring means to a main memory when said valdiity signal indicates that said prediction is correct and for invalidating said execution result data and said write address stored in said storing means when said validity signal indicates that said prediction is incorrect.
A data processor comprising:
- decode means for decoding a plurality of instructions;
- a plurality of operation means each for outputting operation result data for a decoded instruction and a condition code determined by said operation result data;
- supplying means for sequentially supplying said plurality of operation means with said instructions decoded by said decode means, each instruction being supplied to one operation means, said supplying means including means for outputting a number of the operation means to which an instruction has been last supplied;
- and
- branch instruction execution means connected to said decode means for receiving a branch instruction decoded by said decode means, a number corresponding to an operation means outputted from said number outputting means, and a plurality of condition codes repsectively outputted from said operation means, said branch instruction execution means including means for determining whether or not a branch condition of said branch instruction is satisfied based on the condition code outputted from the operation means corresponding to said number.
Dependencies are inferred from the claim text.