US 4,759,043 AGranted

CMOS binary counter

AssigneeRaytheon Company

InventorEdward T. Lewis

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Abstract

A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.

Claims14

Dependent claims

A binary counter having a plurality of sequentially coupled stages, each one of said stages comprising:

a flip-flop means having a data input and an output for providing a counter stage output in response to a clock signal, said flip-flop means being enabled by a count enable signal;
a modulo-two summer means having a first input and an output coupled respectively to said flip-flop means output and data input in said stage and a second input coupled except in a first stage to a carry signal from a previous stage for performing an exclusive-or function on said first input and said second input, said second input in a first stage of said counter being coupled to said count enable signal;
and
a gating means except in a last one of said stages having a first input coupled except in said first stage to said carry signal from a previous counter stage gating means output and a second input coupled to said flip-flop means output in said counter stage for passing said first input when said second input is asserted, said first input in said first stage being coupled to said count enable signal, said gating means having an output coupled to said second input of said modulo-two summer means of the next succeeding counter stage.

1 more element

A binary counter having a plurality of concatenated sections comprising:

a plurality of binary counter stages in each of said sections for performing a counting function by successive additions of a lowest order carry signal input provided by a count enable signal to a first stage of a first section of said binary counter;
means coupled between each pair of said counter sections for generating a carry-forward signal to the succeeding one of said sections;
each of said binary counter stages comprising:
(a) flip-flop means having a data input and an output for providing a counter stage output in response to a clock signal, said flip-flop means being enabled by a count enable signal;
(b) modulo-two summer means having a first input and an output coupled respectively to said flip-flop means output and data input in said counter stage and a second input coupled except in said first stage of each of said sections to a carry signal from a previous stage for performing an exclusive-or function on said first input and said second input, said second input in said first stage of said first section being coupled to said count enable signal and said second input in a first stage of a second section and successive sections being coupled to said carry-forward signal from an immediately preceding section;
and
(c) gating means except in a last stage of each one of said sections having a first input coupled except in said first stage to said carry signal from a previous counter stage gating means output and a second input coupled to said flip-flop means output in said counter stage for passing said first input when said second input is asserted, said first input in said first stage of said counter being coupled to said count enable signal, said gating means having an output coupled to said second input of said modulo-two summer means of the next succeeding counter stage.

4 more elements

Dependencies are inferred from the claim text.