Back to results
US 4,757,275 AGranted
Wideband closed loop amplifier
AssigneeComlinear Corporation
InventorsKenneth R. Saller, Michael A. Steffes
Life of this patent
Estimating the term…
Abstract
A wideband closed loop amplifier is described which has improved accuracy over prior amplifiers. The closed loop amplifier includes (a) first and second differential amplifiers, (b) floating bias means connected between the output terminals of the first and second differential amplifiers, (c) an output stage including first and second output transistors; and (d) first and second bias sources connected to the collector terminals of the respective output transistors.
Claims13
A closed loop buffer amplifier having an input terminal and an output terminal, said amplifier comprising:
- (a) first and second differential amplifiers, each of which includes an inverting input and a non-inverting input and an output;
- (b) floating bias means connected between said output terminals of said first and second differential amplifiers;
- (c) an output stage comprising first and second output transistors each having base, emitter and collector terminals;
- (d) first and second bias sources;
- wherein said first bias source is connected to said collector terminal of said first output transistor;
- wherein said second bias source is connected to said collector terminal of said second output transistor;
- wherein said non-inverting inputs of said first and second differential amplifiers are connected together to form said input terminal of said closed loop buffer amplifier;
- wherein said inverting inputs of said first and second differential amplifiers are connected together to form said output terminal of said closed loop buffer amplifier;
- wherein said emitter terminals of said first and second output transistors are connected to said output terminal of said closed loop buffer amplifier;
- wherein said output of said first differential amplifier is connected to said base terminal of said first output transistor;
- and wherein said output of said second differential amplifier is connected to said base terminal of said second output transistor.
8 more elements
A closed loop buffer amplifier having an input terminal and an output terminal, said amplifier comprising:
- (a) first and second differential pairs, each of which includes non-inverting and inverting inputs and positive and negative outputs;
- (b) first and second current mirrors each having input and output terminals;
- (c) floating bias means connected between said positive output of said first differential pair and said positive output of said second differential pair;
- (d) an output stage comprising first and second output transistors each having base, emitter and collector terminals;
- (e) first and second bias means adapted to bias said output transistors;
- wherein said input terminal of said first current mirror is connected to said negative output of said first differential pair;
- wherein said output terminal of said first current mirror is connected to said positive output of said first differential pair;
- wherein said input terminal of said second current mirror is connected to said negative output of said second differential pair and wherein said output terminal of said second current mirror is connected to said positive output of said second differential pair;
- wherein said non-inverting inputs of said first and second differential pairs are connected together to form said input terminal of said closed loop buffer amplifier;
- and wherein said inverting inputs of said first and second differential pairs are connected together with said emitter terminals of said first and second output transistors to form said output terminal of said closed loop buffer amplifier;
- wherein said base terminal of said first output transistor is connected to said positive output of said first differential pair;
- wherein said base terminal of said second output transistor is connected to said positive output of said second differential pair;
- and wherein said collector terminal of said first output transistor is connected to said first bias means for proper biasing of said first output transistor;
- wherein said collector terminal of said second output transistor is connected to said second bias means for proper biasing of said second output transistor.
11 more elements
Dependencies are inferred from the claim text.