US 4,753,896 A · Sidewall channel stop process

Abstract

A new way of making sidewall channel stops for silicon on insulator devices (including silicon on oxide, silicon on nitride, and silicon on sapphire devices). While the moat regions 11, 13 (where the active devices will be formed) are covered by thick masking material 24, a high energy implantation step introduces additional doping into exposed silicon regions 14'. Before the mesa etch is performed to isolate the individual active device regions 32 a filament 28 is formed on the walls of the masking material 24 which covers the predetermined locations of the active device regions 32. The mesa etch is then performed using a chemistry which will be blocked not only by the original masking material 24 but also by the sidewall filaments 28. Thus, the doping level defined by implantation into regions 14' will extend into the sidewalls of the mesas 32 for a distance which is controlled not only by the lateral diffusion length of those dopants, but also by the thickness of the sidewall filament 28.

Claims49

Dependent claims

A process for fabricating a semiconductor-on-insulator integrated circuit structure, comprising the steps of:

(a) providing a substrate having at a surface thereof a layer of monocrystalline semiconductor material overlying a layer of an insulator;
(b) providing a patterned masking layer over said monocrystalline semiconductor layer, said masking layer being patterned to cover predetermined portions of said semiconductor layer where active devices are to be formed;
(c) implanting a dopant substantially into at least some of the portions of said semiconductor material which are not covered by said masking layer;
(d) forming sidewall insulation filaments on said patterned masking layer, so that said patterned masking layer with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone, but does not cover all of said semiconductor layer;
(e) etching away at least some portions of said monocrystalline semiconductor material to form separated mesas of said monocrystalline semiconductor material on said insulator;
and
(f) fabricating active devices in said mesas.

4 more elements

A process for fabricating a semiconductor-on-insulator device, comprising the steps of:

(a) providing a substrate having at a surface thereof a layer of monocrystalline semiconductor material overlying a layer of an insulator;
(b) providing a patterned masking layer over said monocrystalline semiconductor layer, said masking layer being patterned to cover predetermined portions of said semiconductor layer where active devices are to be formed;
(c) implanting a channel stop dopant substantially into portions of said semiconductor material which are not covered by said masking layer;
(d) forming sidewall insulation filaments on said patterned masking layer, so that said patterned masking layer with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone, but does not cover all of said semiconductor layer;
(e) etching away said semiconductor material except where substantially covered by said masking layer and/or said sidewall filaments on said masking layer, said etching step leaving semiconductor mesas separated by areas of said insulator;
(f) providing a dielectric covering at least some portions of said semiconductor mesas;
and
(g) forming a patterned thin film of conductive material, said patterned thin film of a conductive material providing gates of field effect transistors having channel regions in said mesa.

5 more elements

A process for fabricating a semiconductor-on-insulator device, comprising the steps of:

(a) providing a substrate having at a surface thereof a layer of substantially monocrystalline semiconductor material comprising silicon overlying a layer of an insulator;
(b) providing a patterned masking layer over said monocrystalline semiconductor layer, said masking layer being patterned to cover predetermined portions of said semiconductor layer where active devices are to be formed;
(c) implanting a p-type channel stop dopant into some portions of said semiconductor material which are not covered by said masking layer;
(d) forming sidewall insulation filaments on said patterned masking layer, so that said patterned masking layer with said filaments covers a larger fraction of said semiconductor layer than was covered by said masking layer alone, but does not cover all of said semiconductor layer;
(e) etching away said semiconductor material except where substantially covered by said masking layer and/or said sidewall filaments on said masking layer, said etching step leaving semiconductor mesas separated by areas of said insulator;
(f) providing a dielectric covering at least some portions of said semiconductor mesas;
and
(g) forming a patterned thin film of conductive material, said patterned thin film of a conductive material providing gates of n-channel field effect transistors having channel regions in ones of said mesas which include an admixture of dopant atoms introduced by said channel stop implanting step around the periphery thereof, and also of p-channel field effect transistors having channel regions in others of said mesas.

5 more elements

Dependencies are inferred from the claim text.

Sidewall channel stop process

Life of this patent

Sidewall channel stop process

Life of this patent

Abstract

Claims49