US 4,751,497 AGranted

Digital to analog converter with high output compliance

AssigneeIwatsu Electric Co., Ltd.

InventorToshihiro Torii

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Abstract

The disclosure relates to a digital to analog converter capable of suppressing "glitches" or transient spikes in the analog output signal. The digital to analog converter includes a plurality of current switches corresponding to the number of digital input bit signals and a resistive ladder of the conventional R-2R configuration. The R-2R ladder network has a plurality of input ports each connected to the output of a corresponding current switch. Logic inputs to the current switches determine which of the current switches are to be turned on to supply reference currents to corresponding input ports of the ladder network which in turn decrements the received reference currents by a factor of 2 as they pass through each stage to provide an analog output signal at the output terminal of the converter. To improve the accuracy of D/A conversion of the invention, compensating capacitors affording delay time equalization are provided for the least and most significant bit positions as well as between each two adjacent bit positions. These compensating capacitors operate to compensate for the stray capacitance of each current switch due to the parasitic collector-base capacitance of switching transistors to thereby equalize the impedance of the ladder network as viewed from each input port of the ladder network to the output terminal of the converter.

Claims7

Dependent claims

means for affording impedance equalization to provide an identical time delay for the outputs of the current switches flowing through the respective input ports to the output port of the network;
wherein each current switch comprises a balanced transistor switching means having two branches each including a switching transistor and operated by the reference current, the switching transistor in one branch receiving the digital input bit signal and the switching transistor in the other branch receiving a threshold adjustment voltage, the switching of transistors being alternately turned on to switch the reference current between the two branches in response to the digital input bit signal, the stray capacitance of each current switch resuting from the parasitic collector-base capacitance of the switching transistor in the other branch.

In a digital to analog converter for converting digital input signals, each including a plurality of bits, to corresponding electrical analog output signals, comprising a plurality of current switches corresponding to the number of bits of the digital input signals and selectively rendered conductive in response to digital input bit signals of a given digital input signal, means for supplying a reference current to the plurality of current switches and an R-2R ladder network having a plurality of input ports each being connected to the output terminal of a corresponding current switch and an output port, the R-2R ladder network comprising a plurality of resistors of value R each being connected betwen two adjacent ones of the input ports, a resistor of value R connected between the input port for the least significant bit and a common potential point, a resistor of value R connected between the input port for the most significant bit and the common potential point, and a plurality of resistors of value 2R each being connected between a corresponding one of the input ports associated with the bit position except the least and most significant bits and the common potential point, the input port for the most significant bit serving as the output port of the R-2R ladder network, the ladder network receiving the outputs of the current switches when the ladder are rendered conductive and decrementing the respective current switch outputs as they flow toward the output port to produce an analog output signal for each digital input signal, each current switch having a stray capacitance of value C between its output terminal and the common potential point, which capacitance causes variations in the impedance of the R-2R ladder network as viewed from each input port toward the output port, the improvement comprising:

means for affording impedance equalization to provide an identical time delay for the outputs of the current swtiches flowing through the respective input ports to the output port of the network, said impedance equalization means further comprising
first and second compensating capacitors of value C connected between the input ports for the least and most significant bits respectively, and the common potential point, and
a plurality of third compensating capacitors of value 2C each being connected and parallel to a corresponding one of the R resistors connected between two adjacent ones of the input ports of the R-2R ladder network.

Dependencies are inferred from the claim text.