Processor utilizing reconfigurable process segments to accomodate data word length
OwnerDonald M. Chiarulli, W. G. Rudd +1inventors
InventorsDonald M. Chiarulli, W. G. Rudd, Duncan A. Buell
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Abstract
An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are interconnected so as to form dynamically reconfigurable segments of arithmetic-logic units within the array. These dynamically reconfigurable segments are formed by particular combinations of the arithmetic-logic units and are so combined with selective switching circuitry so as to provide the processor with its independent and parallel features.
Claims6
A method of operating an electronic computer processor having a plurality of ALU's which may be operated in combination to increase their effective word length comprising the steps of:
- (a) synchronizing two or more of said ALU's;
- (b) connecting two or more of said ALU's according to a field in a single instruction word, whereby each group of connected ALU's and each isolated ALU define a segment having a data word length equal to the combined word length of each ALU in said segment;
- (c) entering a separate operation code and a separate operand instruction for each of said ALU's, said operation codes and said operand instructions being contained in a field in said single instruction word;
- (d) generating a local status output for each of said ALU's;
- (e) converting each of said local status outputs to a binary status bit;
- (f) resolving said binary status bits into a single-bit condition code;
- (g) selecting a common, next instruction word address for said ALU's based upon a status of a condition enable code which directs whether said selection is to be made unconditionally or whether said selection is to be made conditioned upon a status of said single-bit condition code.
Dependencies are inferred from the claim text.