Skew error correction circuit for video signal reproducing apparatus

A skew correction circuit for correcting a skew error included in an input signal, said input signal being a video signal which is recorded on and reproduced from tracks on a magnetic tape at each predetermined interval, said track for recording being formed on the tape at a predetermined inclination by a plurality of rotary heads, the video signal thus recorded and reproduced having a skew error such that a time base changes stepwise, comprising:

• (a) separation means for separating synchronization information included in said input signal;
• (b) a write clock signal generating circuit means for generating write clock signals, including an oscillation circuit generating write clock signals, a reference signal generating circuit generating a reference signal, a phase comparator circuit for comparing the reference signal of said reference signal generating circuit or a frequency-divided signal thereof with said write clock signal of said oscillation circuit or a frequency-divided signal thereof so as to output a phase error signal corresponding to a phase difference as the comparison result, voltage control means for voltage controlling the oscillation frequency of said oscillation circuit, and feedback means for negatively feeding back said phase error signal to said voltage control means;
• (c) synchronization information supplying means for injecting said separated synchronization information to said oscillation circuit to synchronize the phase of starting of oscillation by said oscillation circuit with the phase of said synchronization information and for controlling the oscillation for an interval when the injected synchronization is absent;
• (d) read clock signal generating circuit for generating read clock signals having a stable frequency;
• (e) a memory in which said input signal sequentially sampled is written in accordance with said write clock signals and is then sequentially read out in accordance with said read clock signals;
• (f) counter means for counting said write clock signals and outputting a signal indicating the termination of sampling when the count reaches a predetermined value;
• (g) head switching signal receiving terminal means for receiving a head switching signal for controlling the timing of switching of said plurality of rotary heads, and
• (h) latch means connected with said counter means and said head switching signal receiving terminals means for latching the head switching signal by the sampling termination signal from said counter means, and for generating a latched head switching signal, whereby said plurality of rotary heads are switched sequentially in accordance with the latched head switching signal.