Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters

Apparatus comprising:

• a plurality of component circuits, each of said circuits being coupled to a signal conduit path and selectively needing to transmit information onto the signal conduit path, and each of said component circuits being integrated in a separate semiconductor chip;
• a plurality of arbitration conduit paths;
• a carrier, each of the chips being coupled thereto or being a part thereof, a body portion of the carrier and a body portion of at least some of the chips being essentially of the same semiconductor material;
• each of the component circuits assigned a priority with respect to transmission of information onto the signal conduit path;
• each of the component circuits, except for possible the component circuit having the lowest priority, including a separate one of a plurality of arbitration request circuits;
• each arbitration request circuit coupled to a separate one of a plurality of arbitration conduit paths for selectively enabling a signal from its component circuit to reach the signal conduit path coupled thereto;
• each of the component circuits, except for possibly the component circuit having a highest priority, including a separate one of a plurality of arbitration resolution circuits;
• each arbitration resolution circuit coupled to at least one of the arbitration conduit paths to detect whether any of the other component circuits having a higher priority is requesting access to the signal conduit path and to enable its component circuit to gain access to the signal conduit path if its component circuit is requesting access to the signal conduit path and if its component circuit has a higher priority than any other component circuit which is requesting such access;
• a clock conduit path which is coupled to each of the component circuits;
• each arbitration request circuit comprising a first transmission gate element having a control terminal which is coupled to the clock conduit path and having first and second output terminals which are separately coupled respectively to a portion of the component circuit which determines if the component circuit desires access to the signal conduit path and, except for possibly the one such transmission gate element in the component circuit of lowest priority, to a separate one of the arbitration conduit paths;
• each arbitration resolution circuit including a separate binary logic gate, or the equivalent thereof, which has a number of input terminals equal to at least the number of component circuits of higher priority;
• each of the input terminals of the logic gate coupled to a separate one of the arbitration conduit paths or to a node which is connected to a potential level;
• and
• each arbitration resolution circuit further including a latch circuit element and a second transmission gate element having a control terminal which is coupled through an inverter to the clock conduit path and having first and second output terminals which are separately coupled respectively to an output terminal of the logic gate and to an input terminal of the latch circuit element.