Master/slave sequencing processor with forced I/O

An array processor for processing data, comprising:

• a control processor for generating sequencing commands to control instruction flow in the array processor;
• first, second and third slave address processors connected to said control processor and each having internal instructions therein, for receiving the sequencing commands to sequence through the internal instructions in response thereto, the internal instructions at each of said slave address processors sequencing in parallel and synchronously to generate addresses and control signals;
• said first slave address processor receiving a separate one of the sequencing commands;
• said second and thrid slave address processors both receiving a common one of the sequencing commands separate from said first slave address processor, said first and second slave address processors operating in either an 1/0 mode or a data processing mode in response to a predetermined sequence command such that only one of said second and third slave address processors is operating in the I/O mode, wherein the processor operating in the I/O mode is not responsive to further sequencing commands and operates independent of said control processor;
• first, second and third data memories having data input/output ports and connected to each of said first, second and third slave address processors, respectively, for storing data therein, said data memories operating in response to addresses and control signals to either output stored data or receive data for storage therein;
• an array data processor for receiving data on input ports and processing received data in accordance with a predetermined data processing function for output of results on an output port;
• switch means having memory ports interfaced with the data input/output ports of said data memories, processor ports interfaced with the data input/output ports such that the input/output are interfaced with an external I/O device for transfer of data therebetween, said switch means for interconnecting said input/output ports to either said array data processor ports or said I/O ports in a predetermined configuration in accordance with a select one of a connectivity patterns stored in a connectivity register, said select patterns selected in response to the sequencing commands from said control processor, with only said second and third data memories inteconnected with said I/O ports;
• said second and third slave address processors are controlled by the sequencing commands to operate such that one thereof is forced to the I/O mode of operation and the other thereof is in the data processing mode and operates on the sequencing commands, the one thereof in the forced I/O mode controlling the connected data memory for receiving data from the external I/O device or transferring data thereto, wherein completion of an I/O operation, wherein data is completely transferred from or stored in a data memory changes a status of said data memories, said control processor forcing the other of said second and third slave address processor into the I/O mode when the status changes.

A method for processing data and interfacing with an external I/O device, comprising:

• storing data processing instructions at a first slave node, a first set of data processing instructions at a second slave node, and a first set of I/O instructions at the second slave node;
• generating sequence commands at a master node for controlling instruction execution at the slave nodes;
• receiving the sequence commands at each of the slave nodes to sequence through select one of the instructions to generate address and control signals for data processing functions in response to execution of the stored data processing instructions, the instruction sequenced sunchronously with the sequence commands;
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• initiating execution of the I/O instructions at the second slave node in response to select ones of the sequence commands to generate I/O addresses and control signals, execution of the I/O instructions being independent of the sequence commands after initiation thereof;
• providing data memories at the first and second slave nodes and an I/O memory at the second slave node;
• addressing the data memories in response to generation of addresses and control signals at the first and second slave nodes and addressing the I/O memory of the second slave node in response to I/O addresses and control signals generated at the second slave node, addressing of the data memories allowing receipt and storage of data from a data port or output of data to the data port;
• interconnecting the data memories with a data processor and interfacing the I/O memory with an external I/O port for interfacing with the external I/O device for data transfer therebetween;
• processing input data received at the data processor in accordance with a predetermined data processing function and outputting results therefrom for storage in one of the data memories;
• and
• providing status to the master node indicating whether an I/O operation is complete at the second slave node.