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US 4,745,310 AGranted
Programmable delay circuit
AssigneeMotorola, Inc.
InventorMavin C. Swapp
Life of this patent
Estimating the term…
Abstract
A monolithically integrated delay circuit is provided that comprises a gate coupled for receiving a digital input signal. The output of the gate is capacitively loaded whereby the output signal has a sloping downward transition. A line receiver has a first input coupled to said gate and a second input coupled for receiving an analog signal for comparing the analog signal with the output of the gate and for providing a digital output signal that is delayed with respect to the digital input signal.
Claims18
A monolithically integrated delay circuit comprising:
- a first input terminal for receiving a digital input signal;
- a second input terminal for receiving an analog input signal;
- an output terminal for providing an output signal;
- first means coupled to said first input terminal for providing a modified digital signal in response to said digital input signal, said modified digital signal comprising a pulse having a leading edge and a trailing edge, said leading edge and said trailing edge having a different transition time, said first means comprising:
- a first voltage terminal;
- a second voltage terminal;
- an NPN transistor having a base coupled to said first input terminal, a collector coupled to said first voltage terminal, and an emitter;
- a current source coupled between said emitter and said second voltage terminal;
- and
- second means coupled between said output terminal and both said emitter of said NPN transistor and said second input terminal for comparing said modified digital signal and said analog signal and providing an output signal at said output terminal that is delayed in time from said digital input signal.
7 more elements
A monolithically integrated delay circuit comprising:
- a first input terminal for receiving a digital input signal, said digital input signal comprising a pulse having a leading edge and a trailing edge, said leading edge and said trailing edge having a different transition time;
- a second input terminal for receiving an analog input signal;
- an output terminal;
- a first gate;
- a last gate;
- and
- a plurality of gates coupled in series between said first gate and said last gate, said first gate having a first input coupled to said first input terminal, each of said plurality of gates and said last gate having a first input coupled to an output of the preceding gate in series, each of said plurality of gates and saif first and last gates having a second input coupled to said second input terminal, said last gate coupled to said output terminal for providing an output signal.
4 more elements
A delay circuit comprising:
- a first input terminal for receiving a digital input signal, said digital input signal comprising a pulse having a leading edge and a trailing edge, said leading edge and said trailing edge having a different transition time;
- a second input terminal for receiving an analog input signal;
- an output terminal;
- a first gate;
- a last gate;
- a plurality of gates coupled in series between said first and last gates, wherein said first gate has a first input coupled to said first input terminal, eac of said plurality of gates and said last gate having a first input coupled to a first output of the preceding gate in series, each of said plurality of gates and said first and last gates having a second input coupled to said second input terminal, selected ones of said plurality of gates having a second output;
- and
- second means having an output for providing said output signal and having a plurality of inputs, each of said plurality of inputs coupled to one of said first or second outputs of said plurality of gates, for selecting one of said inputs as said output signal.
5 more elements
A programmable delay circuit comprising:
- a first input terminal for receiving a digital input signal;
- a second input terminal for receiving a first analog signal;
- an output terminal for providing an output signal;
- first means coupled to said first input terminal for selectably delaying said digital input signal in selectable first increments for providing a first delayed signal;
- second means coupled to said first means and said second input terminal for comparing said first delayed signal and said first analog signal and providing a plurality of second delayed signals that are selectively delayed in selectable second increments;
- and
- a first multiplexer coupled for receiving a first plurality of programming signals and coupled between said second means and said output terminal for receiving said second plurality of delayed signals and providing one of said second plurality of delayed signals as said output signal in response to said first plurality of programming signals.
4 more elements
A programmable delay circuit comprising:
- a first input terminal for receiving a digital input signal;
- a second input terminal for receiving an analog signal;
- an output terminal for providing an output signal;
- first means coupled to said first input terminal for selectably delaying said digital input signal in selectable first increments for providing a first delayed signal;
- second means coupled to said second input terminal and said first means for selecting one of either of said analog input signal or said first delayed signal for providing a second signal, said second signal comprising a pulse having a leading edge and a trailing edge, said leading edge and said trailing edge having a different transition time;
- and
- third means coupled between said output terminal and both said second means and said second input terminal for comparing said second signal and said analog signal and providing said output signal at said output terminal that is selectively delayed in selectable second increments.
4 more elements
Dependencies are inferred from the claim text.