Method for fabricating MOS transistors having gates with different work functions

A method for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of:

• providing a semiconductor substrate lightly doped with an impurity;
• forming a layer of gate dielectric material on the semiconductor substrate;
• forming a layer of semiconductor material on the gate dielectric material layer;
• providing a pattern of masking material on the layer of semiconductor material, through which selected areas of the layer of semiconductor material are exposed;
• introducing an impurity of a first conductivity type into the selected areas of the semiconductor material layer;
• diffusing the impurity of the first conductivity type in the selected areas of the semiconductor material layer a selected distance into the semiconductor material layer laterally under the masking material pattern, wherein the selected distance is less than that required to completely dope the semiconductor material under the masking layer, leaving a central portion of the conductive material pattern undoped with the impurity of the first conductivity type;
• removing the selected areas of the semiconductor material to leave a gate of semiconductor material having end portions and the central portion between the end portions, the end portions being lightly doped with the impurity of the first conductivity type;
• and
• providing an impurity of a second conductivity type in the central portion.

A process for fabricating an insulated gate field effect transistor (IGFET) comprising the steps of:

• providing a monocrystalline silicon substrate lightly doped with an impurity of a first conductivity type;
• forming a layer of gate silicon oxide on the silicon substrate;
• forming a layer of undoped polycrystalline silicon on the gate silicon oxide layer;
• providing a pattern of masking material on the layer of polycrystalline silicon, through which selected areas of the layer of polycrystalline silicon are exposed;
• introducing an impurity of the first conductivity type into the selected areas of the polycrystalline silicon layer;
• diffusing the impurity of the first conductivity type in the selected areas of the polycrystalline silicon layer a selected distance into the polycrystalline silicon layer laterally under the masking material pattern;
• removing the selected areas of the polycrystalline silicon to leave a polycrystalline silicon gate having end portions and a central portion therebetween, the end portions being lightly doped with the impurity of a first conductivity type;
• and
• introducing an impurity of a second conductivity type into the central portion of the gate and the silicon substrate using the gate as mask to simultaneously form a heavily doped central portion and heavily doped source/drain regions respectively, of a second conductivity type.