Geometric-arithmetic parallel processor

A data processing cell for processing single bits of digital data comprising:

• a full adder having first and second data input terminals, a carry input terminal, a sum output terminal and a carry output terminal;
• an addressable, multi-bit memory having a data input terminal, a data output terminal and a plurality of address terminals;
• bus selector means for selectively applying an output signal from the output terminal of said multi-bit memory or the output signal from the sum output terminal of the full adder to a data bus in response to a first control signal;
• means for selectively applying the output signal from the multi-bit memory or a bus output signal from the data bus to the input terminal of the multi-bit memory in response to a second control signal;
• a carry input accumulator for selectively applying a carry output signal from the carry output terminal or a desired logic level to the carry input terminal of the full adder in response to a third control signal;
• a first data input accumulator means for selectively applying a first data input signal, second data input signal or a bus input signal from the data bus to one of first and second data input terminals of the full adder in response to a fourth control signal;
• and,
• a second data input accumulator means for selectively applying a third data input signal, a fourth data input signal or said bus input signal to the other of said first and second data input terminals of the full adder in response to a fifth control signal, said full adder, said memory and said accumulators being connected such that said full adder performs both arithmetic and logical operations in response to said control signals.

A data processing cell for processing digital data signals comprising:

• a full, one bit adder having first and second data input terminals, a carry input terminal, a sum output terminal and a carry output terminal;
• a single bit carry memory connected to the carry input terminal of the adder;
• a first single bit data memory connected to one of the first and second data input terminals of the adder;
• a second single bit data memory connected to the other of the first and second data input terminals of the adder;
• a random access memory having a data input terminal and a data output terminal;
• a data bus;
• bus selector means for selectively applying one of a plurality of single bit data signals, including the output signal from the random access memory output terminal and the output signal from the adder sum output terminal, to the data bus in response to a first control signal;
• means for selectively applying one of a plurality of single bit data signals, including the output signal from the adder carry output terminal and a desired logic level, to the single bit carry memory in response to a second control signal;
• means for selectively applying one of a plurality of single bit data signals, including the signal stored by the first single bit data memory, the signal on the data bus, and the output signals from two cell input terminals, to the first single bit data memory in response to a third control signal;
• and
• means for selectively applying one of a plurality of single bit data signals, including the signal stored by the second single bit data memory, the signal on the data bus, and the output signals from two cell input terminals, to the second single bit data memory in response to a fourth control signal, whereby said full adder performs both logical and arithmetic operations in response to said control signals.

A data processing cell for processing single bit, digital signals comprising:

• a full adder having first and second data input terminals, a carry input terminal, a sum output terminal, and a carry output terminal, the full adder producing signals at said output terminals related to the arithmetic result of first, second and third input signals applied to said first, second and carry input terminals, respectively;
• a plurality of digital signal memories connected to said first, second and carry input terminals of said full adder each for selectively storing one of a plurality of single bit data input signals as said first, second and third input signals, respectively, in response to a plurality of control signals;
• and,
• an addressable, multi-bit memory having an output terminal providing, from an addressed memory location, one of the plurality of single bit data input signals,
• the full adder and the memories being interconnected and controlled by said control signals so that the full adder performs both arithmetic and logical operations with said plurality of single bit data input signals.

A data processing cell for processing single bit, digital signals comprising:

• a full adder/subtractor having first and second data input terminals, a carry input terminal, a sum output terminal, a carry output terminal, and a borrow output terminal, the full adder/subtractor producing signals at said output terminals related to the arithmetic result of first, second and third input signals applied to said first, second and carry input terminals, respectively;
• a plurality of digital signal memories connected to said first, second and carry input terminals of said full adder/subtractor each for selectively storing one of a plurality of single bit data input signals as said first, second and third input signals, respectively, in response to a plurality of control signals;
• and,
• an addressable, multi-bit memory having an output terminal providing, from an addressed memory location, one of the plurality of single bit data input signals,
• the full adder/subtractor and the memories being interconnected and controlled by said control signals so that the full adder/subtractor performs both arithmetic and logical operations with said plurality of single bit data input signals.

A data processing cell for processing single bits of digital data in a parallel processor array comprising:

• a full adder having first and second data input terminals, a carry input terminal, a sum output terminal and a carry output terminal;
• a carry input accumulator means for selectively applying a first data signal or a desired binary ONE or binary ZERO logic level to the carry input terminal of the full adder in response to a first control signal;
• a first data input accumulator means for selectively applying a second data input signal to one of first and second data input terminals of the full adder in response to a second control signal;
• and,
• a second data input accumulator means for selectively applying a third data input signal to the other of said first and second data input terminals of the full adder in response to a third control signal,
• said full adder and said accumulators being connected such that said full adder performs both arithmetic and logical operations in response to said control signals, said logical operations including at least a logical OR operation and a logical AND operation, the results of said logical OR and AND operations being taken from the carry output terminal of the full adder.

A data processing cell for processing digital data signals comprising:

• a full, one bit adder having first and second data input terminals, a carry input terminal, a sum output terminal and a carry output terminal;
• a single bit carry memory connected to the carry input terminal of the adder;
• a first single bit data memory connected to one of the first and second data input terminals of the adder;
• a second single bit data memory connected to the other of the first and second data input terminals of the adder;
• first and second cell input signal lines operatively connected to an input terminal of the first single bit data memory;
• third and fourth cell input signal lines operatively connected to an input terminal of the second single bit data memory;
• first and second cell output signal lines operatively connected to an output terminal of the first single bit data memory;
• third and fourth cell output signal lines operatively connected to an output terminal of the second single bit data memory;
• and,
• means for selectively applying one of a plurality of single bit data signals, including the output signal from the adder carry output terminal, a binary ONE logic level, and a binary ZERO logic level to the single bit carry memory in response to a control signal, whereby said full adder can perform both logical and arithmetic operations.

A data processing cell for processing single bit, digital signals comprising:

• a full adder having first and second data input terminals, a carry input terminal, a sum output terminal, and a carry output terminal, the full adder producing signals at said output terminals related to the arithmetic result of first, second and third input signals applied to said first, second and carry input terminals, respectively;
• first, second, and third digital signal memories connected, respectively, to said first, second and carry input terminals of said full adder to store said first, second and third input signals, respectively, in response to a plurality of control signals;
• and,
• an addressable, multi-bit memory having an output terminal providing, from an addressed memory location, a data output signal, said output terminal being operatively connected to at least two of said digital signal memories,
• the full adder and the memories being interconnected and controlled by said control signals so that the full adder performs both arithmetic and logical operations.

A parallel data processor having a plurality of cells for processing digital data signals, comprising:

• a controller for generating control signals in response to program instructions;
• and,
• a plurality of identical interconnected cells each including:
• a full adder/subtractor having first and second data input terminals, a carry input terminal, a sum output terminal, a carry output terminal, and a borrow output terminal;
• and,
• first, second and third data storage means connected, respectively, to the first input terminal, the second input terminal, and the carry input terminal of said full adder/subtractor,
• each of said first, second, and third data storage means being connected to said controller, the data storage means each being individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of said full adder/subtractor in response to control signals from the controller, the memories being connected to the full adder/subtractor and the controller such that both logical and arithmetic operations are performed by the full adder/subtractor, the logical operations including at least an OR operation and an AND operation.