Loading patent…
AssigneeMagnavox Government and Industrial Electronics Company
InventorsDavid A. Rowe, Binneg Y. Lao, Robert E. Dietterle
Estimating the term…
A multilayered integrated circuit chip carrier has a top layer, a signal line layer, a ground layer, a power conductor layer, and a bottom layer with a separating layer between adjacent layers. Each layer has coplanar conductive and dielectric portions, the separating layers being primarily dielectric. The top layer supports an integrated circuit chip and signal launcher pads on the bottom layer couple signal and power lines of a printed circuit board to spaced points about the bottom layer periphery and substantially constant signal line impedance is achieved. The signal line layer is separated from the power conductor layer by a ground plane layer. Conductive via through pads are placed in the separating layers to form a plurality of separate conductive paths from each of the bottom and top layers to each of the signal line and power conductor layers. Via through pads are also placed in the separating layers to break up cavities and thus increase cavity resonance above signal frequencies and are placed in the signal line layer to provide signal line isolation. Thermal columns of via pads in the separating layers and conductive portions in the other layers under the chip provide chip cooling. Large grounded conductive areas in the top and bottom layers reduce unwanted signal coupling to the external environment. A capacitive coupling on the top layer between a power conductor and ground provides power line isolation.
Carrier apparatus for an integrated circuit chip having power and signal terminals, the carrier apparatus adapted to be mounted on a printed circuit board comprising:
Apparatus for use with a printed circuit board comprising:
Dependencies are inferred from the claim text.