Electronic musical instrument

A digital system for generating electronic waveforms useful in synthesizing sound comprising an array of bit serial processing elements, each element comprising a digital multiplier, a switching matrix for point to point connection of data between pairs of processing elements wherein each pair may be selected from any two processing elements in said array to allow inputs and output of said elements to be interconnected in discretionary configurations specified by control bits in a communication control word, a programmed digital computer for producing communication control words in response to control command signals, and means for generating said command signals, wherein said digital multiplier is comprised of a plurality of stages connected in series for bit serial multiplication of two numbers, logic means for one bit multiplication of a multiplicand M by a multiplier B, means for storing a carry, C, a three input adder for producing a one bit result a.sub.i+ l and a carry by adding the result of the one bit multiplier logic means with the carry from the last bit result and the result a.sub.i from a preceding stage, or input A in the case of the first stage which may be any number including zero, and including means in each stage for storing one bit of said multiplier, B, as said multiplier is entered serially with each multiplier bit of successively higher order stored in a separate stage of higher order, and means for delaying said multiplicand, M, one bit in each stage as said multiplier is passed serially through said stages to perform the multiplication operation serially, each multiplicand bit being multiplied by every multiplier bit in sequence, and the results of the multiplications in each stage are added to the results of its preceding stage, wherein the last stage is coupled to its preceding stage by an inverter, and the end result Y is coupled out of the last stage through an inverter to accommodate two's complement numbers for the multiplier B, multiplicand M and result Y.

In a digital multiplier comprised of a plurality of stages connected in series for bit serial multiplication of two numbers, logic means for one bit multiplication of a multiplicand M by a multiplier B, means for storing a carry, C, a three input adder for producing a one bit result a.sub.i+1 and a carry by adding the result of the one bit multiplier logic means with the carry from the last bit result and the result a.sub.i from a preceding stage, or an input A in the case of the first stage which may be any number including zero, means in each stage for storing one bit of said multiplier, B, as said multiplier is entered serially with each multiplier bit of successively higher order stored in a separate stage of higher order, means for delaying said multiplicand, M, one bit in each stage as said multiplier is passed serially through said stages to perform the multiplication operation serially, each multiplicand bit being multiplied by every multiplier bit in sequence, and the results of the multiplications in each stage are added to the results of its preceding stage, and said logic means in each stage for one bit multiplication is comprised of a multiplexer controlled by a bit of said multiplicand, M, to select as an input to said adder a bit of said multiplier, B, or a bit of another number, D, and including means in each stage for storing one bit of said other number as said other number is entered serially with each multiplier bit of successively higher order stored in a stage of higher order, whereby linear interpolations between said multiplier and said other number is carried out with the same efficiency as multiplication with said multiplicand being the interpolation constant.

The combination of

• an array of universal processing elements, each comprising pipelined means for computing at least A+(B.times.M), where B is a multiplier, M is a multiplicant and A is an input number to be added to the product B.times.M, and
• a switching matrix for selectively connecting point to point universal processing elements, and for connecting multipliers, multiplicands and input numbers from an external source or other universal processing units to selected universal processing elements wherein said matrix comprises a plurality of conductors, some of which are available for selective connection to every universal processing unit, whereby the output of any one may be connected as an input to anay other, others of which are available only for connection among assigned groups of universal processing usnits, said matrix further comprising means for connections between adjacent universal processing units, each of said universal processing units comprises pipeline means for computing A+[(B.times.M)+D.times.(1-M)] where B and D are n-bit two's complement numbers, and M and A are 2n-bit two's complement numbers, wherein each of n pipelined stages of each universal processing unit is comprised of an adder for computing the sum of A plus a Boolean logic function, [b.multidot.m+d.multidot.m], and a multiplexer responsive to the multiplicand for forming the function [b.multidot.m+d.multidot.m], where a, b, d and m are bits of the respective two's complement number A, B, D and M, whereby the entire array of stages in a universal processing unit computes A+[B.times.M+D.times.(1-M)].