Interrupt mechanism for multiprocessing system having a plurality of interrupt lines in both a global bus and cell buses
AssigneeInternational Business Machines Corporation
InventorsSumit DasGupta, John M. Hancock, James H. Kukula, Roger E. Peo
Life of this patent
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Abstract
A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.
Claims4
In a multiprocessing system, the combination comprising:
- a global bus having a plurality of interrupt lines;
- an executive processor connected to said global bus for signalling interrupt requests on predetermined interrupt lines;
- a plurality of cells connected to said global bus, each cell being connected to receive an interrupt request from a different one of said predetermined interrupt lines;
- each cell comprising
- a cell bus having a plurality of interrupt lines,
- and a plurality of cell processors each connected to a different one of said interrupt lines of said cell bus for receiving interrupt requests therefrom one cell processor is a master processor for receiving interrupt requests initiated by said executive processor, and each other cell processor in a cell is a slave processor for receiving interrupt requests from said master processor;
- the total number of cell processors exceeding the number of interrupt lines in said global bus, whereby each cell processor has a unique interrupt by virtue of each cell being connected to a different interrupt line in said global bus and each cell processor being connected to a different interrupt line in said cell bus connected thereto;
- said executive processor initiating an interrupt request for a given slave processor in one of said cells, such interrupt request being transmitted over said global bus by the one of said interrupt lines thereof connected to said one cell, to said master processor in such cell, said master processor in such cell responding to receipt of such interrupt request to transmit such interrupt request to said given slave processor;
- and memory means connected to the global bus and each of said cell processors for storing interrupt handling routines;
- each cell processor in response to an interrupt request received on an interrupt line of said cell bus connected thereto, to interrupt its current processing and process one of said interrupt handling routines.
Dependencies are inferred from the claim text.