Microprogram-coupled multiple-microprocessor module with 32-bit byte width formed of 8-bit byte width microprocessors

A microprogram-coupled multiple-microprocessor module comprising:

• a data processing unit including a plurality of microprocessors each having an internal data bus and a program counter, a plurality of corresponding main data busses, the main data busses combining in parallel to form a module data bus, and a control circuit coupling said microprocessors to said main data busses;
• an address processing unit for keeping track of memory addresses that correspond to the data processed in the microprocessors of the data processing unit, including at least one microprocessor having a microprocessor address bus and a microprocessor data bus;
• means coupling the microprocessor address bus to a module address bus;
• data transfer means coupling the microprocessor data bus of said at least one microprocessor to a stack pointer bus and to the internal data bus of at least one of the microprocessors of the data processing unit;
• and APU logic mapping means coupled to one of said main data busses of the data processing unit and to said at least one microprocessor of the address processing unit for op code mapping of said at least one microprocessor of the address processing unit according to a predetermined op code mapping scheme stored in said APU logic mapping means;
• a stack pointer processing unit external to said at least one microprocessor of said address processing unit for keeping track of stack pointers for all microprocessors, including address processor control means and data transfer means coupling the address processor control means to the stack pointer bus of the address processing unit and to the internal data bus of said one of the microprocessors of said data processing unit;
• and
• a microprogram control and signalling unit including microprogram memory means storing microinstructions to be applied to said microprocessors of said data processing unit;
• microinstruction sequencing logic means providing address data to said microprogram memory means to determine the next successive address of a microprogram sequence, and flag and signal generating circuit means having inputs coupled to the internal data busses of the microprocessors of the data processing unit and outputs providing status flags and signals to said microinstruction sequencing logic means to control the synchronization of the microinstructions executed in the multiple microprocessors of said data processing unit and the at least one microprocessor of said address processing unit so that memory fetch and memory write operations are all synchronized;
• such that the microprogram control and signalling unit controls the data processing unit, the address processing unit, and the stack pointer processing unit by delaying the incrementation of one or more of the program counters of the microprocessors of the data processing unit as need be so that the several microprocessors of the data processing unit and the address processing unit complete corresponding operations at the same time, and so that carries are accounted for from one of the microprocessors of the data processing unit to another thereof.