Interleaved set-associative memory

A set-associative cache memory comprising:

• a plurality of memory parts each including a plurality of memory locations each for storing a word of information, the locations of the plurality of memory parts being grouped into a plurality of levels and each level having a location from each of the memory parts, each location of a level for storing any word of a plurality of words associated with that level, the plurality of parts defining a plurality of sets of frames, each frame defined by a plurality of locations each from a different level, a frame of each set for storing any block of words of a plurality of blocks, each block having a plurality of words each associated with a different level;
• means for storing a plurality of words of a block simultaneously into one of the associated frames, each word in a location of the associated level and of a different memory part;
• and
• means for checking for presence of a desired word simultaneously in all locations of the level associated with the desired word.

A two-way set-associative two-way interleaved cache memory comprising:

• a pair of memory parts each comprising a plurality of storage locations each for storing a word of information, the locations of one memory part defining even locations of a first cache set of a plurality of locations and odd locations of a second cache set of a plurality of locations and the other memory part defining odd locations of the first cache set and even locations of the second cache set, the locations of the pair of memory parts being grouped into at least four levels and each level having a location from each of the memory parts and each of the cache sets;
• means for receiving simultaneously a first pair of contiguous words of a block of four contiguous words, and for receiving simultaneously a second pair of contiguous words of the block;
• means for storing one pair of the received words simultaneously into locations of one cache set, each word into a location of a different memory part and of a different level of first and second levels, and for storing the other pair of received words simultaneously in locations of the one cache set, each word into a location of a different memory part and of a different level of third and fourth levels;
• and
• means for simultaneously checking all locations of a level for presence therein of a desired word.

A processing system comprising

• a main memory for storing a plurality of words of information,
• a cache memory for storing selected ones of the main memory words, and
• a communication bus for transferring simultaneously a plurality of words from the main memory to the cache memory,
• the cache memory comprising:
• a plurality of memory parts each including a plurality of memory locations each for storing a word, the locations of the plurality of memory parts being grouped into a plurality of levels and each level having a location from each of the memory parts, each location of a level for storing any word of a plurality of words associated with that level, the plurality of parts defining a plurality of frames, each frame defined by a plurality of locations each from a different level, a frame for storing any block of words of a plurality of blocks, each block having a plurality of words each associated with a different level;
• means for receiving from the bus a plurality of words simultaneously;
• means for storing the received words simultaneously, each word into a location of the associated level and of a different memory part;
• and
• means for checking for presence of a desired word simultaneously in all locations of the level associated with the desired word.

A processing system comprising

• a main memory for storing a plurality of words of information,
• a set-associative cache memory for storing selected ones of the main memory words, and
• a communication bus for transferring simultaneously a plurality of words from the main memory to the cache memory,
• the cache memory comprising:
• a plurality of memory parts each including a plurality of memory locations each for storing a word, the locations of the plurality of memory parts being grouped into a plurality of levels and each level having a location from each of the memory parts, each location of a level for storing any word of a plurality of words associated with that level, the plurality of parts defining a plurality of sets of frames, each frame defined by a plurality of locations each from a different level, a frame of each set for storing any block of a plurality of blocks associated with those frames, each block having a plurality of words;
• means for receiving from the bus a plurality of words of a block simultaneously;
• means for storing the received words simultaneously into one of the associated frames, each word into a location of the associated level and of a different memory part;
• and
• means for checking for presence of a desired word in all locations of the level associated with the desired word simultaneously.

A processing system comprising

• a main memory for storing a plurality of blocks of four contiguous words of information,
• a two-way set-associative two-way interleaved cache memory for storing selected ones of the main memory blocks, and
• a communication bus for transferring in parallel a pair of words of a block from the main memory to the cache memory,
• the cache memory comprising:
• a pair of memory parts each comprising a plurality of memory locations each for storing a word, the locations of one memory part defining even locations of a first cache set of a plurality of locations and odd locations of a second cache set of a plurality of locations and the other memory part defining odd locations of the first cache set and even locations of the second cache set, the locations of the pair of memory parts being grouped into at least four levels and each level having a location from each of the memory parts and each of the cache sets;
• means for receiving simultaneously from the bus a first pair of contiguous words of a block, and for receiving simultaneously a second pair of contiguous words of the block;
• means for storing one pair of the received words simultaneously into locations of one cache set, each word into a location of a different memory part and of a different level of first and second levels, and for storing the other pair of received words simultaneously in locations of the one cache set, each word into a location of a different memory part and of a different level of third and fourth levels;
• and
• means for simultaneously checking all locations of a level for presence therein of a desired word.