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AssigneeTexas Instruments Incorporated
InventorsRonald B. Jennings, Donald P. Shaver, Maurice A. T. Ward, Eric A. Parsons, Philip T. Mueller, Jr.
Estimating the term…
A general purpose array processor is made up of a plurality of independent processing units. A digital host computer provides the overall control for the system. An interface unit is connected to receive instructions and data signals from the host computer and then to autonomously and selectively distribute the instructions and data to other units within the system and to transmit status, control and data signals to the digital host computer. A transfer controller unit is connected to a bulk memory and to the interface unit for receiving the instructions from the interface unit and for autonomously and selectively transferring data signals from the bulk memory means to an arithmetic unit which is also connected to the interface means and receives instructions therefrom for subsequently autonomously and selectively performing arithmetic functions on the data transferred by the transfer controller unit. An input controller unit may be provided for receiving data from a data source. The input controller unit is connected to the other units and to the bulk memory and receives the data from the source of data and reformats and transmits the reformatted data to the bulk memory. The arithmetic unit has a fixed point and a floating point adder for flexiblility of operation.
An array processor system having bulk memory means, for storing data,, controlled by digital host computer means, comprising:
An array processor system having bulk memory means for storing data, controlled by digital host computer means, comprising:
Dependencies are inferred from the claim text.
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Implementation of control logic, e.g. test mode decoders: using microprogrammed units, e.g. state machines
Single instruction multiple data [SIMD] multiprocessors: one dimensional arrays, e.g. rings, linear arrays, buses
Response verification devices: using compression techniques
Static stores
Term ended 22 Nov 2005 (estimated)
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A microfiche appendix of 215 pages and 4 microfiche is part of the specification but not printed therewith.
1. Field of the Invention
This invention relates to a general purpose array processor and more particularly to an array processor made up of autonomously operating units, including a fixed point and floating point arithmetic unit that is particularly optimized for performing the Fast Fourier Transform algorithm.
FIG. 1 illustrates the array processor of this invention in place within a data collection and recording system.
FIG. 2 is a block diagram of the array processor invention.
FIG. 3 is a block diagram of any individual device making up the array processor (except PIT).
Because of increasing resolution requirements in seismic exploration and the need to improve productivity and cycle time and delivery of final processed data, an advanced field system for seismic data collection was developed.
A major portion of that system is the array processor described and claimed herein. The array processor achieves very high operational speed through the system architecture which employs a number of individual devices. In this preferred embodiment, these devices are the host interface (HI), the transfer controller (TC), the arithmetic unit (AU), and the input controller (IC). The processor initialization and test (PIT) is still another device, but differing somewhat in structure. These devices are interrelated but are separately programmed via assembly language so that they operate independently of one another, supplying results when required. A bulk memory is connected to the devices for the storage of data originally from a host computer or from a source of seismic data.
FIG. 1 illustrates a data collection and recording system. The array processor (ATPV) 10 is shown as part of the overall array processing system 11. Host computer 12 is shown connected to array processor 10 as is bulk memory coupler 14c to which bulk memories 14a and 14b are connected. Recording control unit 16 is shown connected to line interface unit 17 which in turn is connected to the array processing system for supplying seismic data thereto.