Data processing device
AssigneeHitachi, Ltd.
InventorsYooichi Shintani, Tohru Shonai, Shigeo Takeuchi
Life of this patent
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Abstract
A data processing device which is equipped with a plurality of arithmetic units so that a plurality of instructions may be processed in parallel by the plural arithmetic units. The device includes a register control circuit for assigning one of a plurality of physical registers to store instructions when more than one of the instructions requires the use of the same logical register. This correspondence between the physical and logical registers is maintained while instructions are subsequently transferred to the arithmetic units where they are processed in parallel.
Claims7
A data processing device comprising:
- a plurality of arithmetic units for processing a plurality of instructions in parallel;
- a plurality of first and second registers, for storing both data to be processed by said arithmetic units and the processed results of said arithmetic units;
- a control circuit for dynamically assigning different ones of said second registers to those instructions which designate an identical one of said first registers;
- and means maintaining the corresponding relationship between said first register and said assigned second registers while the instructions are processed in parallel in said arithmetic units.
A data processing device comprising:
- means for inputting instructions;
- a plurality of registers;
- detecting means for detecting when more than one of said instructions requires the use of the same one of said plurality of registers;
- assigning means, responsive to said detecting means, for dynamically assigning a different one of said plurality of registers to store one of the instructions when said same one of said plurality of registers is being used for another instruction;
- transfer means, responsive to said assigning means, for transferring data to selected ones of a plurality of arithmetic units;
- and
- control means, responsive to said assigning means, for controlling said arithmetic units such that the instructions are processed in parallel.
A data processing device comprising:
- means for inputting instructions;
- a plurality of registers;
- detecting means for detecting when more than one of said instructions requires the use of the same one of said plurality of registers;
- assigning means, responsive to said means for detecting, for dynamically assigning a different one of said plurality of registers to store one of the instructions when said same one of said plurality of registers is being used for another instruction;
- and
- control means for controlling the transfer of data between said means for assigning and one of a plurality of arithmetic units such that said instructions are processed in parallel.
Dependencies are inferred from the claim text.