Dynamic CMOS current surge control
AssigneeAmerican Telephone and Telegraph Company, AT&T Bell Laboratories
InventorsChe-Tsung Chen, Kevin D. Kolwicz, Chin-Jen Lin, Won J. Yoon
Life of this patent
Estimating the term…
Abstract
Integrated circuits having a large number of transmission gate logic stages have been found to draw a large current surge on power-up. This is due to the floating input node of complementary inverters causing current to flow briefly before clock pulses arrive. The present invention provides a DC voltage on the gates of the pass transistors until the system clock pulses arrive, thereby eliminating the floating node. An optional periodic window may be generated to examine the system clock after power-up, to detect a loss of clock condition.
Claims8
An integrated circuit comprising transmission gate logic circuitry, means for receiving a system clock signal from a system clock, and means for providing multi-phase clock signals to the gates of pass transistors connected to complementary inverters in said logic circuitry,
- characterized in that said integrated circuit further comprises control circuitry that causes DC voltages to be applied to said gates so as to cause said pass transistors to conduct when the power supply voltage is applied to said integrated circuit, and to thereafter cause said multi-phase clock signals to be applied to said gates when said system clock signal is detected.
Dependencies are inferred from the claim text.