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US 4,736,117 AGranted
VDS clamp for limiting impact ionization in high density CMOS devices
AssigneeNational Semiconductor Corporation
InventorJames B. Wieser
Life of this patent
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Abstract
A circuit for controlling drain-to-source voltage in an MOS transistor. A second MOS transistor is located in series with the first transistor. The gate voltage of the second transistor is such that the drain-to-source voltages of both transistors are substantially equal.
Claims2
In a switched capacitor filter amplifier of the type that includes
- (a) a power supply for generating a first voltage and a second voltage;
- (b) an input stage including
- (i) a differential transistor pair having source elements connected to a common node which is at a substantially fixed voltage,
- (ii) a current mirror,
- (iii) a pair of common gate load transistors coupled in series between the respective drains of the differential transistor pair and the current mirror, the gates of the load transistors having a bias potential applied thereto;
- and
- (c) an inverting amplifier stage which receives a single-ended output from the input stage, the inverting amplifier stage including
- (i) a driver transistor connected to the power supply, and
- (ii) a current sink biased in parallel with a tail current sink for the differential transistor pair,
- the improvement comprising a clamping transistor located in series with the driver transistor and having its gate connected to the common node of the differential transistor pair such that the drain-to-source voltages of the driver transistor and the clamping transistor are substantially equal.
7 more elements
Dependencies are inferred from the claim text.