FET for high reverse bias voltage and geometrical design for low on resistance

A method for constructing a filed-effect transistor device at an outer major surface of a first semiconductor material body of a first conductivity type, said method comprising:

• providing a first electrical insulating layer of a first thickness on said outer major surface, at least at a first major surface portion, said first insulating layer having a first insulating layer major surface on a side thereof opposite that side thereof which is in contact with said first major surface portion;
• providing a first gate region on at least a portion of said first insulating layer major surface across said first insulating layer from less than all of said first major surface portion;
• providing at least two lesser conductivity terminating region portions of a second conductivity type in said semiconductor material body intersecting said first major surface portion and spaced apart in said first major surface portion to thereby form at least two spaced apart intersection surfaces in said outer major surface, there being pn junctions resulting about each of said lesser conductivity terminating region portions separating these regions from remaining portions of said first semiconductor material body with these said pn junctions intersecting said first major surface portion to form a boundary about each of said intersection surfaces in said first major surface portion, said first gate region being directly across said first insulating layer from that space in said first major surface portion separating said two intersection surfaces;
• providing a second electrical insulating layer of a second thickness on said first gate region and extending beyond said first gate region to be across from substantially all of each said lesser conductivity terminating region portion, said second insulating layer having a second insulating layer major surface on a side thereof opposite that side thereof which is in contact with said first gate region;
• providing a first shield region on at least a portion of said second insulating layer major surface across from said first gate region and across from each of said lesser conductivity terminating region portions, but across from less than all of each of said lesser conductivity terminating region portions at least by virtue of a plurality of openings each provided through said first shield region and across from a contact surface located entirely within each said intersection surface;
• and
• providing higher conductivity terminating region portions of said second conductivity type in said semiconductor material body intersecting said first major surface portion at each of said contact surfaces across from each corresponding said opening in said first shield region, said higher conductivity terminating region portions having a conductivity occurring therein exceeding that occurring in those said lesser conductivity terminating region portions remaining after said providing of said higher conductivity terminating region portions.