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US 4,735,913 AGranted
Self-aligned fabrication process for GaAs MESFET devices
AssigneeBell Communications Research, Inc.
InventorJohn R. Hayes
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Abstract
A self-aligned process for fabricating a GaAs semiconductor MESFET by depositing a layer of tungsten over the GaAs substrate, and ion implanting the substrate to provide channel doping. A gate composed of a conductive refractory material is deposited and delineated on the tungsten layer, and source and drain regions are formed in the substrate using the gate as a mask. The resulting device is annealed and contacts are formed to the source and drain regions, and to the gate.
Claims5
A self-aligned process for fabricating a semiconductor MESFET device comprising the steps of:
- providing a semiconductor substrate;
- depositing a layer of tungsten over said substrate;
- ion implanting said substrate with a dopant species through said layer of tungsten to provide channel doping;
- depositing a platinum-gold layer;
- depositing a masking layer over said platinum-gold layer;
- patterning said platinum-gold layer defined by said masking layer to form a gate etch mask;
- forming source and drain regions in said substrate using said gate etch mask as a mask;
- annealing said device;
- selectively removing portions of said tungsten layer to form a gate using said gate etch mask region as a mask;
- and
- forming electrical contacts to said source region, to said drain region, and to said gate.
8 more elements
Dependencies are inferred from the claim text.