Semiconductor memory

A semiconductor memory of a redundant design comprising:

• a memory cell array in which a plurality of memory cells are regularly arrayed along a plurality of word lines and a plurality of bit lines perpendicular to said word lines and an arbitrary one of said memory cells can be specified by the combination of a column address and a row address,
• reading means for selecting one of said word lines by said row address to read out onto said bit lines, an information charge of the memory cells connected to said selected one of said word lines,
• means for selecting one of said bit lines by said column address to provide to a device located external to said semiconductor memory the information charge amplified by said sense amplifier connected to said selected one of said bit lines, and
• a spare column decoder for selecting a spare bit line when a column address corresponding to a defective bit line is applied,
• said semiconductor memory being characterized in that a plurality of charging means are provided in said spare column decoder, each said charging means comprising a switched constant voltage source.