Circuit arrangement comprising a matrix shaped memory arrangement for variably adjustable time delay of digital signals

A circuit arrangement for providing a variably adjustable time delay for a data stream of digital signals, comprising:

• a memory matrix including a plurality of storage elements arranged in columns and rows, each of said storage elements comprising a three-transistor cell having overlapping write/read cycles, a separate write bit line and a separate read bit line for each column respectively connected to each cell of the respective column, and a separate write word line and a separate read word line for each row respectively connected to each cell of the respective row;
• a reset control signal input for receiving a reset control signal;
• a continuously steppable clocked row selector including a plurality of cascaded selector stages each including two mutually offset signal outputs respectively connected to a respective write word line and a respective read word line and each including a control input connected to said reset control signal input for receiving a reset signal at an arbitrary time for setting the first stage and resetting all other stages of said row selector;
• an undelayed data output and a plurality of delayed data outputs;
• a data input for receiving an input data stream to be delayed, said data input connected to said write bit line of a first of said columns and to said undelayed data output;
• and
• a plurality of amplifiers each assigned to a respective column including an input connected to a respective read bit line of the respective column and an output connected to a respective delayed data output and to said bit write line of the adjacent column,
• the spacing between reset signals selected to be equal to the desired delay between said undelayed data output and the delay output of the first column.