US 4,734,882 AGranted

Multilevel interrupt handling scheme

AssigneeHarris Corporation

InventorAlfredo A. Romagosa

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Abstract

An interrupt request handling mechanism employs a portion of the address portion of the data processing system's communication bus. All interrupt requests to a processor are handled by an associated interrupt controller that is coupled between the prescribed address lines and the processor. As interrupt requests are received they are temporarily stored in memory. The storage locations of the memory are successively scanned, beginning with the memory address having the highest priority level and proceeding through successively lesser orders of priority locations until an interrupt request has been found. That located "highest" priority level interrupt request that is stored in memory is placed in a buffer register the contents of which are compared, on a continual basis, with the level of the task being executed by the processor. Upon the level of the task under execution by the processor falling below that associated with the contents of the buffer register, the interrupt controller couples the contents of the buffer register to the processor as an interrupt. When the processor acknowledges capture of the interrupt from the interrupt controller, the corresponding storage location in memory is erased.

Claims12

Dependent claims

For use with a data processing system wherein interrupt requests for service by a processing device are transmitted over a processor communication link, each interrupt request having a prescribed level of priority, an arrangement for controllably coupling interrupt requests to said processing device comprising:

random access memory means, coupled to said processor communication link and having a plurality of addressable storage locations, for storing, sequentially in time, interrupt requests supplied over said communication link in accordance with the order in time that said requests are supplied thereto and in memory address locations associated with the respective levels of priority of said requests;
memory address scanning means, coupled to said random access memory means, for scanning the storage locations of said random access memory means to locate a stored interrupt request whose priority level among requests stored by said random access memory means is highest;
register means for controllably storing an interrupt requests;
and
comparison means, coupled to said processing device and to said register means, for comparing the contents of said register means with the level of task execution activity of said processing device and, upon detecting the level of task execution activity of said processing device to be less than the priority level as represented by the contents of said register means, causing the contents of said register means to be forwarded to said processing device as an interrupt request.

2 more elements

Dependencies are inferred from the claim text.