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AssigneeAdvanced Micro Devices, Inc.
InventorsWilliam M. Johnson, Rod G. Fleck, Cheng-Gang Kong, Ole Moller
Estimating the term…
A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, a channel data register which temporarily stores the data from a store operation and, a channel control register which contains control information including the number of the register loaded within the file, in the case of a load operation. This number is used to detect instruction dependency of the data to be loaded. Logic circuitry suspends further instruction processing if the data required from a load is not yet available. A data-in register is used to store load data until an instruction execution cycle is available for writing it back to the register file. Logic circuitry detects storage of data prior to its writing back, so as to effectively replace the register file location. During page faults, the contents of the channel address, channel data, and channel control registers are saved to permit page fault recovery.
A digital processor control which cyclically executes instructions from a set including a load from memory and a store to memory instruction and provides instruction execution simultaneously with access to a memory, comprising:
A method of executing instructions by a digital processor which are retrieved from an instruction cache, each instruction including a plurality of operands, said instruction executed simultaneously with accesses to a memory, said digital processor having a digital processor control which has a file of registers each having a location designator, comprising the steps of:
A method of recovering from a memory page faulted by a digital processor which cyclically executes instructions each including a plurality of operands from a set including a load data instruction and a store data instruction, which has a memory having a plurality of memory locations each having an address and a file of registers each having a location designator, comprising the steps of:
Dependencies are inferred from the claim text.