Decoupling capacitor for surface mounted leadless chip carrier, surface mounted leaded chip carrier and pin grid array package

An electronic subassembly comprising:

• a surface mountable leadless integrated circuit chip carrier package, said leadless chip carrier package having an array of conductive connecting means arranged exteriorly on the perimeter thereof, at least some of the connecting means being first and second voltage level connecting means;
• a circuit board, said circuit board having conductive pads thereon receiving said connecting means from said leadless chip carrier package;
• and
• decoupling capacitor means, said decoupling capacitor means being mounted over and aligned with said leadless chip carrier package and electrically communicating with said circuit board, said capacitor means comprising;
• at least one multilayer capacitor chip having interleaved layers of conductive material and dielectric material with alternating layers of conductive material being electrically connected and defining first and second groups of conductive layers, each of said first and second groups having at least one exposed conductive layer defining a first exposed conductive layer and a second exposed conductive layer;
• first conductive layer means associated with ceramic substrate means and in electrical contact with said first exposed conductive layer and defining a first voltage level conductive layer means;
• second conductive layer means associated with ceramic substrate means and in electrical contact with said second exposed conductive layer and defining a second voltage level conductive layer means;
• a plurality of first leads in a predetermined configuration in electrical contact with said first conductive layer means and extending outwardly therefrom;
• a plurality of second leads in a predetermined configuration in electrical contact with said second conductive layer means and extending outwardly therefrom;
• and
• the configurations of said first and second leads corresponding to configurations of first and second voltage levels of connecting means of said leadless chip carrier package.