Circuit for multiplying a pump clock voltage
AssigneeHughes Aircraft Company
InventorFrank J. Bohac, Jr.
Life of this patent
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Abstract
A voltage multiplier circuit is disclosed. The circuit comprises three p-channel MOS transistors and three capacitors. When these elements are connected to properly phased transfer and pump clock signals of positive polarity, the circuit generates a negative output voltage which is roughly equal in magnitude to the peak-to-peak voltage of the pump clock. One of the transistors couples the output node to the circuit input node, and is clocked by the transfer clock so as to isolate the input node from the output node when the output node potential is lower than the input node potential. Several of the circuits may be cascaded to produce a large negative supply from a small positive supply. The circuit is advantageously employed to provide the programming signal supply for EEPROM devices.
Claims22
A voltage multiplier circuit having an input node and an output node, comprising:
- transfer clock means for providing a transfer clock signal;
- pump clock means for providing a pump clock signal having high and low levels;
- pump capacitor means for capacitively coupling said pump clock means to said output node;
- switching means for selectively coupling the output node to or isolating it from the input node in response to said transfer clock signal so that said switching means couples said input node to said output node during an interval when said pump clock is at said high level to equalize the potential between said input and output nodes, and to isolate said nodes when the potential at the output node is lower than the potential at the input node.
A voltage multiplier circuit having an input node and an output node, comprising:
- transfer clock means for providing a transfer clock signal;
- pump clock means for providing a pump clock signal having high and low levels;
- pump capacitor means for capacitively coupling said pump clock means to said output node;
- and
- switching means for selectively coupling the output node to the input node in response to said transfer clock signal, said switching means comprising transistor means having first and second electrodes coupled respectively to said input and output nodes, and a control gate capacitively coupled to said transfer clock means;
- whereby said transfer clock signal and said switching means are cooperatively adapted so that said switching means couples said input node to said output node during an interval when said pump clock signal is at said high level so as to equalize the potential between said first and second node, and isolates said input and output nodes when the potential at the output node is lower than the potential at the input node.
A voltage multiplier circuit for responding to nonoverlapping first and second pump clock signals, each having high and low levels, and nonoverlapping first and second transfer clock signals, each having high and low levels, an output voltage more negative than the low state of the clock signal, said circuit comprising:
- a plurality of cascaded multiplier stages, each stage having an input node and an output node, the output node of the odd ones of the stages being capacitively coupled to receive said first pump clock signal and the output node of the even ones of the stages being capacitively coupled to receive said second pump clock signal, each stage further comprising:
- switching means responsive to one of said first and second transfer clock signals for selectively coupling the output node to the input node during each interval in the cycle of said respective first and second pump clock signals when said respective pump clock signal is at said high level, and for isolating said input node from said output node when said output node is at a potential lower than the potential of said input node.
A voltage multiplier for integrated circuits for generating an output voltage from a pump clock signal having periodic high and low level, comprising at least one stage, each stage comprising:
- pump capacitor means for coupling said pump clock signal to the output node of the stage;
- field effect transistor means having source and drain electrodes coupling said output node to the input node of the stage, and a control gate coupled to receive a transfer clock signal;
- the transfer clock signal being cooperatively arranged with said pump clock signal so as to gate the transistor to the conductive level during the time intervals when said pump clock signal is at its high level to equalize the potential at said input and output nodes, and so that the transistor is in the nonconductive level when the pump clock signal is at its low level;
- whereby each stage of said multiplier circuit is adapted to generate a potential at the output node substantially equal to -(V.sub.H -V.sub.IN), where V.sub.IN represents the potential at the input node and V.sub.H represents the potential of the pump clock signal at the high level.
Dependencies are inferred from the claim text.