Readout circuit for dual-gate CID imagers with charge sharing corrected for subtractive error

In an IR sensitive charge injection device (CID), the combination comprising:

• (A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which m rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line,
• (B) a readout circuit comprising:
• (a) means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS.sub.1-m), for establishing said charge storing potential wells at the row gates and for facilitating charge exchange between column and row gates at a site,
• (b) a source (VRT) of row transfer potentials and m controllable row transfer switches (TS.sub.1-m) for injecting signal charge into the substrate and transfering charge via the column line during readout,
• (c) a shift register (SR) with complementary outputs coupled to said transfer switches and to said row bias reset switches for sequentially connecting a respective (ith), where i is a member of the series 1 to m, single row line to said source (VRT) and disconnecting said (ith) single row line from said source (VRB), the non (ith) row lines remaining connected to said source (VRB), each state thereof defining a pixel readout period,
• (d) n column video processors, each jth processor where j is a member of the series 1 to n, comprising:
• (1) a gain amplifier (A1.sub.j) having the input thereof coupled to the (jth) column line at a first node (N1.sub.j),
• (2) means including a source (VCB) of column bias potentials and a controllable column bias reset switch (S0.sub.j), for applying a column bias potential (VCB) to said first node (N1.sub.j) for establishing said charge storing potential wells at the column gates, and for facilitating charge exchange between column and row gates at a site,
• (3) means for dc restoration comprising a capacitor (C1.sub.j) having one terminal coupled to the output of said gain amplifier, and the other to a second node (N2.sub.j), and a switch (S1.sub.j) having one terminal coupled to said second node (N2.sub.j), and the other coupled to ground,
• (4) means for subtractive error correction comprising a capacitor (C2.sub.j) having one terminal coupled to said second node (N2.sub.j) and the other coupled to a third node (N3.sub.j), and a switch (S2.sub.j) having one terminal coupled to said third node (N3.sub.j) and the other coupled to ground,
• (5) means for obtaining a signal sample comprising a capacitor (C3.sub.j) having one terminal connected to ground and the other terminal providing the output terminal for said jth column video processor, and a switch (S3.sub.j) having one terminal coupled to said third node (N3.sub.j), and the other coupled to the column output terminal, and
• (e) timing means including a timing generator for timing the operation of the scanning shift register (Q.sub.1-m) and the switches, (S0.sub.1-n S1.sub.1-n S2.sub.1-n S3.sub.1-n), the shift register Q.sub.i and switches S0.sub.j, S1.sub.j, S2.sub.j, S3.sub.j, effecting the readout of the site at the ith row jth column,
• said timing means dividing the readout period for each pixel site into a half period for subtractive error correction and a half period for signal sampling,
• said timing means momentarily closing ythe switches S0.sub.j, S1.sub.j and S2.sub.j to begin subtractive error correction, said closings resetting nodes N1.sub.j, N2.sub.j and N3.sub.j to said bias VCB, ground, and ground, respectively, then opening switch S0.sub.j, then opening switch S1.sub.j after settling, to finish charging capacitor C1.sub.j for dc restoration and to begin charging capacitor C2.sub.j, then opening switch S2.sub.j to finish charging capacitor C2.sub.j for subtractive error correction,
• said timing means momentarily closing the switches S0.sub.j and S1.sub.j to begin signal sampling, said closings resetting nodes N1.sub.j and N2.sub.j to said bias VCB and ground, respectively, then opening switch S0.sub.j, then opening switch S1.sub.j after setting to finish charging capacitor C1.sub.j for dc restoration, then closing the ith row transfer switch (TS.sub.i) to inject signal charge into said substrate and to transfer charge to and from the column cells, then momentarily closing switch S3.sub.j to provide an output signal adjusted by the charge on capacitor C1.sub.j for dc restoration and by the charge on capacitor C2.sub.j for subtractive error correction.