Integration time control for a radiation sensitive charge injection device

In an IR sensitive charge injection device (CID), the combination comprising:

• (A) an array comprising a substrate of IR sensitive semiconductor material supporting an interfacing layer of insulating material and on which rows by n columns of pixel sites forming charge storing potential wells are arranged, each site having a conductive row gate and a conductive column gate, the charges at a site being free to flow at the interface between the column gate and row gate in the presence of a bias potential, the row gates for each row of sites being interconnected by a conductive row line and the column gates for each column of sites being interconnected by a conductive column line,
• (B) a readout circuit comprising:
• (a) means including a source (VRB) of row bias potentials and m controllable row bias reset switches (RS.sub.l-m), for establishing said charge storing potential wells at the row gate cells and for facilitating charge exchange between column and row gates at a site,
• (b) a source (VRD) of row dump potentials suitable for injecting signal charge into the substrate and m controllable row dump switches (DS.sub.l-m), each dump switch being connected to couple the dump potential to an associated row site,
• (c) a source (VRR) of row read potentials suitable for injecting signal charge into the substrate and transferring charge via the column line during readout, and m controllable row switches (TS.sub.l-m), each row read switch being connected to couple the read potential to an associated row site,
• (d) means including a clock rate .phi.CK to establish equal charge integration times for all sites comprising
• (1) means including a first m stage shift register (SRD) for propagating at a said clock rate .phi.CK, a given logical state starting in response to a dump start pulse (.phi.SD) recurring at the interval required to sequentially scan said m sites, connected to said means B(b) for sequentially dumping each site when said given logical state occurs and clocked at a given clock rate to produce sequential dump outputs (QD.sub.l-m) having the duration of a clock period,
• (2) means including a second m stage shift register (SRR) for propagating at said clock rate .phi.CK, a given logical state starting in response to a read start pulse (.phi.SR) recurring at the interval required to sequentially scan said m sites, connected to said means B(c) for sequentially reading out each site when the last recited logical state occurs, and clocked at said given clock rate to produce sequential read outputs (Q.sub.Rl-m) having the duration of a clock period,
• (3) m fold means for ANDing/.phi.CK and QD.sub.i to obtain a sequence of single pulses for each row of the duration of the clock pulse highs (QD.sub.i..phi.CK),
• (4) m fold means for ANDing .phi.CK and QR.sub.l-m to obtain a single pulse in the scanning sequence for each row of the duration of said clock pulse highs (QR.sub.i..phi.CK), and which lag said dump pulses at each pixel by an integral number of clock pulses,
• (5) a source of periodic short, dump gate pulses (.phi.GD) at the clock repetition rate,
• (6) a source of periodic short, read gate pulses (.phi.GR) at the clock repetition rate,
• (7) m fold means to AND (QD.sub.i..phi.CK) and (.phi.GD) to obtain a short dump pulse for each row (QD.sub.i..phi.CK..phi.GD), the output thereof being coupled to means B(b) for dumping,
• (8) m fold means to AND (QD.sub.i..phi.CK) and (.phi.GR) to obtain a short read pulse for each row, (QR.sub.i..phi.CK..phi.GR) delayed an integral number of clock pulses from the dump pulse for that row, the output thereof being coupled to means B(c), for readout,
• (9) m fold means for ORing the outputs of means B(d)(8) or B(d)(7) coupled to said means B(a) for disconnecting a row line from said source (VRB), when either dumping or readout is occurring,
• (10) timing means providing said dump start pulses .phi.SD and said read start pulses .phi.SR, said read start pulses being delayed in relation to said dump start pulses by a predetermined portion of the scanning interval required to sequentially scan m sites to establish a desired and equal integration time for each site.