US 4,733,390 AGranted

Data transmission system

AssigneeKabushiki Kaisha Toshiba

InventorsMasakazu Shirakawa, Hiroyuki Hasegawa

Life of this patent

Estimating the term…

Loading patent…

Abstract

A data transmission system in which a plurality of data transmitting circuits with different addresses allotted thereto and a common data receiving circuit are coupled to one another through common data transmission lines. A clock pulse signal determining the rate of data transmission and a frame sync signal determining one frame period having a plurality of time slots are transmitted to the common data transmission lines. The plurality of data transmission circuits are each given a right to transmit data in a plurality of time slots according to a predetermined priority. Each data transmitting circuit is allowed to transmit data in time slots other than a time slot in which a first priority is assigned to itself, after confirming that no data is being transmitted to the common data transmission line by other data transmitting circuits with a priority higher than its priority.

Claims6

Dependent claims

A data transmission system comprising:

a plurality of data transmitting circuit means with different addresses allotted thereto;
common data receiving circuit means;
and
common data transmission line means for coupling said plurality of data transmitting circuit means to said common data receiving circuit means, said common data transmission line means including a first transmission line through which a clock pulse signal determining the rate of data transmission is transmitted, a second transmission line through which a frame sync signal determining one frame period of time having a plurality of time slots and synchronized with said clock pulse signal is transmitted, and a third transmission line through which a data signal is transmitted from each of said data transmitting circuit means to said data receiving circuit means;
said plurality of data transmitting circuit means each being responsive to said clock pulse signal, said frame sync signal and its own allotted address to transmit data to said third transmission line with a first priority in a time slot corresponding to its own allotted address in the frame period of time and to have a right to transmit data to said third transmission line with a priority of a lower order than said first priority in the other time slots, each of said data transmitting circuit means transmitting data after confirming that no data is being transmitted by data transmitting circuit means having a priority of a higher order than its own priority in a time slot, in which it is given a priority of a lower order than said first priority.

2 more elements

A data transmission system comprising:

a plurality of data transmitting circuit means with different addresses allotted thereto;
common data receiving circuit means;
and
common data transmission line means for coupling said plurality of data transmitting circuit means to said common data receiving circuit means, said common data transmission line means including a first transmission line through which a clock pulse signal determining the rate of data transmission is transmitted, a second transmission line through which a frame sync signal determining one frame period of time having a plurality of time slots and synchronized with said clock pulse signal is transmitted, and a third transmission line through which a data signal is transmitted from each of said data transmitting circuit means to said data receiving circuit means;
said plurality of data transmitting circuit means each including time slot counting means for counting time slots in response to said clock pulse signal and said frame sync signal to provide data representing a time slot number k, and priority determining means responsive to the time slot number k data and an address i allotted to itself for determining priority orders to transmit data to said third transmission line in a plurality of time slots, said priority determining means being arranged to determine the priority orders as follows:
(A) i modulo (j)=k modulo (j)
where j represents a parameter, and
(B) addresses of data transmitting circuit means having a priority in the time slot whose number is k are
(1) first priority:
k
(2) second priority:
(k+j) modulo N
(3) third priority:
(k+2j) modulo N
(4) fourth priority:
(k+3j) modulo N
(m) m-th priority:
{k+(m - 1)j} modulo N
where N is the number of time slots in one frame period, m is the maximum number of data transmitting circuit means capable of data transmission in one time slot, and m and j are related by
N=m.times.j.

17 more elements

A data transmission system comprising:

a plurality of data transmitting circuit means having different addresses allotted thereto;
common data receiving circuit means;
and
common data transmission line means for coupling said plurality of data transmitting circuit means to said common data receiving circuit means, said common data transmission line means including a first transmission line through which a clock pulse signal determining the rate of data transmission is transmitted, a second transmission line through which a frame sync signal determining one frame period of time having a plurality of time slots and synchronized with said clock pulse signal is transmitted, and a third transmission line through which a data signal is transmitted from each of said data transmitting circuit means to said common data receiving circuit means;
each of said plurality of said data transmitting circuit means including time slot counting means responsive to said clock pulse signal and said frame sync signal for counting time slots in one frame period of time to provide data representing a time slot number;
priority control circuit means responsive to the time slot number data provided by said time slot counting means and address data representing an address allotted to itself for generating a data transmission permit signal in a plurality of time slots in which a priority to transmit a data signal to said third transmission line is assigned to itself;
transmitting register circuit means for storing a data signal to be transmitted to said third transmission line, said transmitting register circuit means issuing a transmission ready signal upon completion of storing said data signal into said transmitting register means;
and monitoring control circuit means coupled to said priority control circuit means, said transmitting register circuit means and said third transmission line for monitoring said third transmission line and enabling said transmitting register circuit means to transmit said data signal to said third transmission line in response to said transmission permit signal from said priority control circuit means and said transmission ready signal from said transmitting register circuit means when a data signal is not transmitted to said third transmission line from other transmitting circuit means.

5 more elements

Dependencies are inferred from the claim text.