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US 4,733,377 AGranted
Asynchronous semiconductor memory device
AssigneeFujitsu Limited
InventorsKeizo Aoyama, Kenji Agatsuma, Yasuaki Suzuki
Life of this patent
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Abstract
An asynchronous semiconductor memory device having an address change detector which generates a pulse with a specified pulse width by detecting change in an address signal and a component for holding an internal circuit in the non-operating condition responding to the address signal for a period when said pulse does not exist. The internal circuit is caused not to operate in response to an unwanted address signal generated in the course of the change of the address signal input from an external device, or in response to an unwanted address signal generated by noise. Thereby power consumption is reduced.
Claims4
An asynchronous semiconductor memory device comprising:
- an internal circuit for receiving an address signal and operating in response to said address signal, said internal circuit comprising:
- a power supply line for supplying an operating voltage;
- and
- a decoder circuit, connected to said power supply line, for receiving said address signal and said operating voltage and outputting a decoded output signal;
- detecting means, connected to receive said address signal, for detecting a change of said address signal and for generating a respective detection output pulse having a predetermined width corresponding to a specified period;
- and
- holding means, connected to said decoder circuit, for holding said internal circuit in a non-operating condition for said specified period, in response to each said detection output pulse in accordance with each respective change of said address signal, said holding means comprising:
- a first transistor, connected between said power supply line and said decoder circuit, and connected to said detecting means, being controlled by said detection output pulse for disconnecting said decoder circuit and said power supply line for said specified period;
- and
- a second transistor, connected to receive said decoded output signal and connected to said detecting means, being controlled in response to said detection output pulse for grounding said decoder circuit for said specified period.
7 more elements
An asynchronous semiconductor memory device comprising:
- an internal circuit connected to receive an address signal and operating in response to said address signal and including:
- a power supply line for supplying an operating voltage;
- and
- a plurality of transistors, each of said plurality of transistors having a gate supplied with a respective bit of said address signal;
- a first transistor connected to said power supply line;
- and
- a decoder circuit having first, second and third terminals, and an output terminal, for receiving said operating voltage and said address signal and outputting a decoded output signal at said output terminal, said first transistor connected in series between said power supply line and said third terminal and having a gate connected to said first terminal;
- detecting means, connected to receive said address signal, for detecting a change in said address signal and for generating a respective detection output pulse having a predetermined width;
- and
- holding means, connected to said decoder circuit, for holding said internal circuit in a non-operating condition for a specified period corresponding to the predetermined width of said detection output pulse, in response to each said detection output pulse in accordance with each respective change of said address signal, said holding means including:
- a second transistor, connected between said power supply line and said first terminal of said decoder, providing said operating voltage to said first terminal of said decoder in accordance with said detection output pulse;
- a third transistor, connected between said second terminal of said internal circuit and ground, for cutting off the second terminal of said decoder circuit from ground in accordance with said detection output pulse;
- a fourth transistor, connected between said output terminal of said decoder circuit and said third terminal, being controlled in response to said detection output pulse;
- and
- a fifth transistor, connected between said output terminal and ground, for connecting said output terminal to ground in accordance with said detection output pulse, said second and fourth transistors being complementary with respect to said third and fifth transistors.
12 more elements
Dependencies are inferred from the claim text.