Semiconductor memory device having serial data input circuit and serial data output circuit

A semiconductor memory device, comprising:

• a memory cell array including a plurality of memory cells arranged in a matrix and having a plurality of bit lines and a plurality of word lines;
• a serial data input circuit operatively connected to said memory cell array and including:
• at least one shift register set, each having a plurality of shift registers and consecutively storing serial input data applied from an external circuit;
• and
• at least one first gate set, each having a plurality of gates for simultaneously connecting said plurality of shift registers of said at least one shift register set and said plurality of bit lines to store simultaneously said serial input data, stored in said plurality of shift registers, into memory cells selected by one of said word lines;
• and
• a serial data output circuit operatively connected to said memory cell array and including:
• at least one data bus;
• at least one data holding circuit set, each having a plurality of data holding circuits and corresponding outputs, an input of each being operatively connectable to said corresponding bit lines through a corresponding one of said gates of said at least one second gate set;
• at least one third gate set, each having a plurality of gates provided between the outputs of said plurality of said at least one data holding circuit and the at least one data bus and for outputting data held in said at least one data holding circuit to said at least one data bus;
• and
• data output means having a gate driving circuit for selectively driving one of said gates in said at least one third gate set, said plurality of gates of said at least one second gate set being simultaneously operated to transfer a plurality of data on a selected word line into said at least one data holding circuit set, and said data held in said at least one data holding circuit set being output to said at least one data holding circuit set being output to said at least one data bus in response to the operation of said at least one third gate set.