Non-volatile memory circuit

A non-volatile memory circuit having a power source and a high voltage application terminal for writing data, comprising:

• non-volatile memory means coupled between the power source and the high voltage application terminal for storing data;
• voltage limiting means for limiting the voltage applied to the non-volatile memory means, coupled between the power source and the high voltage application terminal;
• and
• current limiting means for limiting the current applied to the non-volatile memory means, coupled between the high voltage application terminal and the non-volatile memory means;
• whereby the non-volatile memory means is protected from erroneous writing of data from outside noise and static noise, wherein the voltage limiting means includes at least one diode and at least one capacitor in parallel with one of said diodes and further including at least one high break-down voltage transistor as said current limiting means and further including at least two series connected high break-down voltage transistors and a capacitor coupled between one of the source and drain of each said high break-down transistor and said power source.

A non-volatile memory circuit having a power source and a high voltage application terminal for writing data, comprising:

• non-volatile memory means coupled between the power source and the high voltage application terminal for storing data;
• voltage limiting means for limiting the voltage applied to the non-volatile memory means, coupled between the power source and the high voltage application terminal;
• and
• current limiting means for limiting the current applied to the non-volatile memory means, coupled between the high voltage application terminal and the non-volatile memory means, wherein the current limiting means includes at least one inductor and at least one resistor in series wherein the resistor and inductor are respectively formed in a P.sup.- well and a parasitic inductance in integrated wiring of the circuit;
• whereby the non-volatile memory means is protected from erroneous writing of data from outside noise and static noise.

A non-volatile memory circuit having a power source and a high voltage application terminal for writing data, comprising:

• non-volatile memory means coupled between the power source and the high voltage application terminal for storing data;
• voltage limiting means for limiting the voltage applied to the non-volatile memory means, coupled between the power source and the high voltage application terminal;
• and
• current limiting means for limiting the current applied to the non-volatile memory means, coupled between the high voltage application terminal and the non-volatile memory means, wherein the current limiting means includes two transistors of like conductivity type, one of the source and drain and the gate electrodes of the first transistor and one of the source and drain electrode of the second transistor being coupled to the high voltage application terminal and the gate and the other of the source and drain electrodes of the second transistor and the other of the source and drain electrode of the first transistor being coupled to the non-volatile memory means;
• whereby the non-volatile memory means is protected from erroneous writing of data from outside noise and static noise.

A non-volatile memory circuit having a power source and a high voltage application terminal for writing data, comprising:

• non-volatile memory means coupled between the power source and the high voltage application terminal for storing data;
• voltage limiting means for limiting the voltage applied to the non-volatile memory means, coupled between the power source and the high voltage application terminal;
• and
• current limiting means for limiting the current applied to the non-volatile memory means, coupled between the high voltage application terminal and the non-volatile memory means, wherein the current limiting means includes a resistor and a capacitor in series between the power source and the high voltage application terminal, an inverter, the input of the inverter being coupled to a point between the resistor and the capacitor, a pair of transistors of opposite conductivity type coupled with their respective source-drain paths in parallel between the high voltage application terminal and the non-volatile memory means, the gate electrode of one of the transistors being coupled to the point between the resistor and the capacitor and the gate electrode of the other transistor being coupled to the output of the inverter wherein the conductance of the transistors as a current limiting means is controlled using the resistor-capacitor time constant circuit;
• whereby the non-volatile memory means is protected from erroneous writing of data from outside noise and static noise.