Dynamic semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTohru Furuyama, Shigeyoshi Watanabe, Tatsuo Ikawa
Life of this patent
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Abstract
A semiconductor memory device has N sense amplifiers each having first and second input terminals, N first memory cells, N second memory cells, N first bit lines each of which is connected to the first memory cells of the same column and connected to the first input terminal of one of the sense amplifiers, and N second bit lines each of which is connected to the second memory cells of the same column and connected to the second input terminal of one of the sense amplifiers. The first memory cells are formed in a first memory cell area and the second memory cells are formed in a second memory cell area arranged adjacent to the first memory cell area and on the same side as the first memory cell area with respect to the sense amplifiers.
Claims10
A dynamic semiconductor memory device comprising:
- a base surface having a sense area and first and second memory cell areas diposed adjacent to each other, each said first and second memory cell areas being adjacent said sense area at one side thereof;
- .sup. N sense amplifiers, N being an integer greater than one (1), disposed within said sense area, each of said amplifiers including a first input terminal and a second input terminal for receiving input signals, each said sense amplifier generating an output signal responsive to said input signals received at said first and second input terminals;
- a plurality of first memory cells arranged in a plurality of rows and columns in said first memory area;
- a plurality of second memory cells arranged in a plurality of rows and columns in said second memory cell area;
- 2.sup.N first bit lines, N being said integer greater than one (1), each of said bit lines being commonly connected to one of said plurality of columns of said first memory cells and connected to said first input terminal of one of said sense amplifiers;
- .sup. N second bit lines, N being said integer greater than one (1), each of said bit lines being commonly connected to one of said plurality of columns of said second memory cells and connected to said second input terminal of one of said sense amplifiers;
- a plurality of first word lines, each of said first word lines being connected to one of said plurality of rows of said first memory cells;
- and
- a plurality of second word lines, each of said second word lines being connected to one of said plurality of rows of said second memory cells.
Dependencies are inferred from the claim text.