US 4,733,371 AGranted

Semiconductor memory device with high voltage switch

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsYasushi Terada, Takeshi Nakayama, Kazuo Kobayashi

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Abstract

A semiconductor memory device according to the present invention includes a first high-voltage switch (20) formed by a first transistor (21), a second transistor (22), a first capacitor (23) and a third transistor (24) and a second high-voltage switch (30) formed by a fourth transistor (31), a fifth transistor (32), a second capacitor (33) and a sixth transistor (34). In a write cycle, input data are stored in capacitors (25, 35). In an erase cycle, the second high-voltage switch (30) is driven by a clock signal (.phi..sub.2) to make the control gate line (4) rise at a high voltage. In a program cycle, the first high-voltage switch (20) is driven by a clock signal (.phi..sub.1) to make the bit line of the bit to be written with data "0" rise at a high voltge, and upon completion of the program cycle, charges stored in the capacitor (25) are discharged to reset a column latch. Thus, the device requires no inverter and may be provided with only one high voltage source.

Claims3

Dependent claims

A semiconductor memory device comprising bit lines, control gate lines, a high voltage source and first and second high-voltage switches,

said first high-voltage switch including:
a first transistor having a drain connected to said high-voltage source and a gate connected to said bit line,
a second transistor having a drain connected to said bit line and a gate and a source connected to the source of said first transistor,
a first capacitor having an end connected to the source of said first transistor and said gate and source of said second transistor, and
a third transistor having a drain connected to the other end of said first capacitor, a gate connected to said bit line and a source applied with a first clock signal,
said second high-voltage switch including:
a fourth transistor having a drain connected to said high voltage source and a gate connected to said control gate line,
a fifth transistor having a drain connected to said control gate line and a source connected to the source of said fourth transistor,
a second capacitor having an end connected to said source of said fourth transistor and said gate and source of said fifth transistor, and
a sixth transistor having a drain connected to the other end of said second capacitor, a gate connected to said control gate line and a source supplied with a second clock signal.

7 more elements

Dependencies are inferred from the claim text.