US 4,733,350 AGranted

Improved purge arrangement for an address translation control system

AssigneeFujitsu Limited

InventorsHirosada Tone, Tsutomu Tanaka

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Abstract

An address translation control system comprising an address translation buffer having a plurality of entries each including at least a valid flag, a logical address field, and a physical address field, a memory array having copies of at least the valid flag and the physical address field, and a purge register for storing information showing a portion of the contents of the address translation buffer to partially purge the address translation buffer. When coincidence between the physical address of the address translation buffer and the contents of the purge register does not occur, ordinary access processing is carried out, and when entry of the memory array is accessed in turn and coincidence between the physical address in the memory array and the contents of the purge register occurs, purge is performed by clearing the valid flags of the corresponding entries of the address translation buffer and the memory array. Thus, purge processing can be carried out separately from the ordinary access processing, and the application efficiency for the address translation buffer increases. Particularly, the performance efficiency for the application of this invention to a pipeline system or a virtual machine can be increased.

Claims7

Dependent claims

An address translation control system comprising:

an access means for accessing an address translation buffer;
said address translation buffer stores a plurality of entries of translated addresses, each of said entries including at least a valid flag, a logical address field and physical address field;
purge register containing a physical address to be purged from said address translation buffer;
first comparator means connected to said address translation buffer and said purge register, said first comparator means for comparing said physical address in said purge register with a physical address read from said address translation buffer, wherein use of said physical address from said address translation buffer is enabled when said first comparator means determines said physical address from said address translation buffer does not coincide with said physical address in said purge register, and use of said physical address from said address translation buffer is inhibited when said first comparator means determines said physical address from said address translation buffer does coincide with said physical address in said purge register;
memory array connected to said address translation buffer, said memory array stores copies of said valid flags and said physical addresses from said address translation buffer;
and
second comparator means connected to said purge register and said memory array, said second comparator means for comparing said physical address in said purge register with a physical address from said memory array, wherein said physical addresses in said memory array are sequentially accessed and compared by said second comparator means, and when said second comparator means determines that said physical address accessed from said memory array coincides with said physical address in said purge register, said coinciding physical address is purged from said address translation buffer and from said memory array.

4 more elements

An address translation control system comprising:

an access means for accessing an address translation buffer;
said address translation buffer stores a plurality of entries of translated addresses, each said entry including at least a valid flag, a logical address field, a physical address field, and a virtual machine identification field;
a purge register containing a physical address to be purged from said address translation buffer;
a purge virtual machine identification register which stores a virtual machine identification to be purged;
a first comparator means connected to said address translation buffer and said purge register, said first comparator means for comparing the address in said purge register with a physical address of a current entry read from said address translation buffer;
a third comparator means being connected to said address translation buffer and said purge virtual machine identification register, third comparator means for comparing a virtual machine identification in said purge virtual machine identification register with a virtual machine identification of said current entry, use of said current entry is enabled when (a) said first means determines said physical address from said address translation buffer does not coincide with said physical address in said purge register and when (b) said third comparator means determines said virtual machine identification from said address translation buffer does not coincide with said virtual machine identification in said purge virtual machine identification register, and use of said current entry is inhibited when (c) said first comparator means determines said physical address from said address translation buffer does coincide with said physical address in said purge register or when (d) said third comparator means determines said virtual machine identification from said address translation buffer coincides with said virtual machine identification in said purge virtual machine identification register;
memory array connected to said address translation buffer, said memory array stores a copy of said valid flag, said virtual machine identification and said physical address from said address translation buffer;
second comparator means connected to said purge register nad said memory array for comparing said physical address in said purge register with a physical addresses read from said memory array;
and
fourth comparator means connected to said purge virtual machine identification register and said memory array, said fourth comparator means for comparing said of virtual machine identification in said purge virtual machine identification register with said virtual machine identification in said memory array, wherein said virtual machine identifications in said memory array are sequentially accessed and compared by said fourth comparator means, when said fourth comparator means determines that one of said virtual machine identifications of said memory array coincides with said virtual machine identification in said purge virtual machine identification register, said coinciding virtual machine identification is purged from said address translation buffer and from said memory array;
said physical addresses in said memory array are sequentially accessed and compared by said second comparator, and when said second comparator determines that one of said physical addresses from said memory array coincides with the physical address in said purge register, said coinciding physical address is purged from said address translation buffer and from said memory array.

8 more elements

Dependencies are inferred from the claim text.