Virtual-memory multiprocessor system for parallel purge operation
AssigneeKabushiki Kaisha Toshiba
InventorsTakashi Hiraoka, Toyohiko Matsushita
Life of this patent
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Abstract
A virtual memory control multiprocessor system has a plurality of processors each having a translation lookaside buffer (TLB). A purge request source processor commonly supplies a purge request signal to other processors so as to cause them to perform TLB purge operations. A purge end signal sent back from other processors is stored in flip-flops in the source processor in units of processors. The source processor detects the end of TLB purge operations of all processors, in accordance with the statuses of the flip-flops.
Claims2
A virtual-memory-type multiprocessor system having a plurality of processors each having a translation lookaside buffer, comprising:
- a first processor having a purge request signal generating means for supplying a common purge request signal requesting purging of translation lookaside buffers of said other processors;
- a plurality of flip-flops provided in each of said plurality of processors each of said flip-flop for storing a corresponding purge end signal, for each of said plurality of processors, each of said other processors, upon completion of purge operations in response to the common purge request signal, sending a corresponding processor number to each other processor;
- each of said processors further comprising:
- a decoder for decoding each processor number sent and setting the flip-flop corresponding to the decoded processor number;
- and
- purge end detecting means connected to each of said plurality of flip-flops for detecting the end of the purging of all processors.
Dependencies are inferred from the claim text.