Data processor with multiple register blocks

A data processing apparatus comprising:

• a memory;
• a plurality of register blocks, each including a plurality of registers and each including state means for setting the corresponding register into one of a plurality of states including a "save" state, in which the corresponding register block supplies data to be saved in said memory for a subroutine call, a "restore" state in which the corresponding register block receives saved data from said memory for a subroutine return, an access state in which the correponding register can be accessed for a subroutine call or return to pass parameters, and a use state;
• program executing means for accessing at least one of said plurality of register blocks and for executing a program including a subroutine call and a return, said program execution means including means, responsive to the program subroutine call and return, for generating a subroutine call signal and a return signal, respectively;
• memory interface means for holding addresses for said memory, responsive to said subroutine call signal and return signal generated from said program executing means, for executing a data transfer between said memory and one of said plurality of register blocks set in the "save" state or the "restore" state, and for generating an end signal upon completion of said data transfer;
• and
• register control means for setting a first one of said plurality of register blocks into said access state thereby allowing access by said program executing means in response to said subroutine call signal or return signal, for selectively setting a second one of said register blocks into said "save" state or "restore" state, and, responsive to said end signal, for selectively setting a third of said plurality of register blocks into said use state for use by said program executing means.