Time-base corrector
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorTakeshi Morimoto
Life of this patent
Estimating the term…
Abstract
A time-base corrector for a video tape recorder capable of slow motion reproduction, in which the time-base correction is effected by the control of write into and read from a memory circuit of digitized reproduction video signal in such a manner that even if a dropout occurs of the vertical sync signal required for address control of the write/read operation, a forecast V signal from a V forecasting circuit is prepared and used thereby to eliminate the vertical fluctuations of the image on the monitor screen completely. It is also possible to produce a high-quality image completely free of the vertical fluctuation even at the time of special reproduction changing in V signal internals.
Claims5
A time-base corrector comprising a memory for storing a reproduction video signal reproduced by a video tape recorder, a write/read address generator circuit for a write and read address for each line to the memory, a sync separator circuit for extracting a reproduction vertical sync signal and a reproduction horizontal sync signal from said reproduction video signal, a vertical sync signal forecasting circuit for counting a predetermined number of a signal synchronous with said reproduction horizontal sync signal and forecasting the position of a reproduction vertical sync signal in the next field, thereby to generate a forecast vertical sync signal, and a vertical sync signal compensation circuit supplied with the reproduction vertical sync signal and the forecast vertical sync signal and normally producing the reproduction vertical sync signal, said vertical sync signal compensation circuit outputting the forecast vertical sync signal in the case of dropout of the reproduction vertical sync signal, wherein the write line address of said memory is latched by the output of said vertical sync signal compensation circuit, and the signal thus latched is loaded as a read line address on the write/read address generator circuit at the position of the vertical sync signal of the external reference sync signal.
A time-base corrector comprising a memory for storing a reproduction video signal reproduced from a video tape recorder, a write/read address generator circuit for generating a write and a read address for each line to said memory, a sync separator circuit for extracting a reproduction vertical sync signal and a reproduction horizontal sync signal from said reproduction video signal, a vertical sync signal forecasting circuit for counting a predetermined number of the signal synchronous with the reproduction horizontal sync signal and generating a forecast vertical sync signal by forecasting the position of the reproduction vertical sync signal in the field next to the reproduction vertical sync signal, a vertical sync signal compensation circuit supplied with the reproduction vertical sync signal and the forecast vertical sync signal and normally producing the reproduction vertical sync signal, said vertical sync signal compensation circuit outputting the forecast vertical sync signal in the absence of the reproduction vertical sync signal, a smoothing circuit for preparing the average data of the present line and the preceding line, and a field identification circuit for identifying the fields of the reproduction video signal and the external reference sync signal, wherein the write line address of said memory is latched at a first vertical reference position obtained from the vertical sync signal of the vertical video signal, the address thus latched is loaded as a read line address on the write/read address generator circuit at a second vertical reference position obtained from the vertical sync signal of the external reference sync signal, and the data from the smoothing circuit is used as read data when the fields of the reproduction video signal and the external reference sync signal are different from each other, selected one of the operation timing of selected one of latching and loading and line address being appropriately shifted by one horizontal scanning period in selected one of the cases where the reproduction video signal is an even-numbered (second, fourth) field and the external reference sync signal is an odd-numbered (first, third) field and where the reproduction video signal is an odd-numbered field and the external reference sync signal is an even-numbered field.
Dependencies are inferred from the claim text.