US 4,733,283 AGranted

GaAs semiconductor device

AssigneeFujitsu Limited

InventorShigeru Kuroda

Life of this patent

Estimating the term…

Loading patent…

Abstract

A method of manufacturing a GaAS semiconductor device of an E/D construction having a GaAs/AlGaAs heterojunction and utilizing a two-dimensional electron gas, which includes the steps of forming a heterojunction semiconductor substrate and etching a portion of the substrate to provide a gate portion of a depletion-mode FET. When the substrate of a semi-insulating GaAs layer, an undoped GaAs, an N-type AlGaAs layer providing an electron-supply layer, and a GaAs layer is formed, the GaAs layer is composed of a first GaAs layer, an etching stoppable AlGaAs layer, and a second GaAs layer, the first GaAs layer being formed on the N-type GaAs layer. The etching for provision of the gate portion is carried out by a dry etching method using an etchant of CCl.sub.2 F.sub.2 gas, so that the second GaAs layer can be etched but the AlGaAs layer cannot be etched. Thus, the thickness of the layers between a gate electrode of the depletion-mode FET and the GaAs/AlGaAs heterojunction plane is determined by the formation of the heterojunction substrate, and consequently a better uniformity of the threshold voltage of depletion-mode FET's is obtained.

Claims6

Dependent claims

A GaAs semiconductor device comprising an enhancement-mode FET and a depletion-mode FET which have a heterojunction and at least one of which utilizes a two-dimensional electron gas, said semiconductor device comprising:

a semi-insulating GaAs substrate;
an updoped GaAs layer formed on said semi-insulating GaAs substrate;
an N-type AlGaAs layer formed on said undoped GaAs layer and including an exposed portion;
a first N-type GaAs layer formed on said N-type AlGaAs layer and having a groove formed therein;
an etching stoppable N-type AlGaAs layer formed on said first N-type GaAs layer;
a second N-type GaAs layer formed on said etching stoppable N-type AlGaAs layer and having a groove formed therein;
a gate electrode of said enhancement-mode FET self-aligningly filling the groove formed in said first GaAs layer and formed on an exposed portion of said N-type AlGaAs layer for providing an electron supply layer for said enhancement-mode FET;
and
a gate electrode of said depletion-mode FET for self-aligning filling a groove formed in said second N-type GaAs layer and formed on an exposed portion of said etching stoppable AlGaAs layer, said etching stoppable layer, said first GaAs layer and said N-type AlGaAs layer providing an electron supply layer for said depletion-mode FET, said gate electrode of said enhancement-mode FET and said gate electrode of said depletion-mode FET being formed simultaneously.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/909,464Filed 19 Sep 1986 · division
Priority: JP 58-4200714 Mar 1983
Granted: 22 Mar 1988
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 30/80
Field-effect transistors [FET]: fETs having rectifying junction gate electrodes
H10D 30/4755
Having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs: having wide bandgap…
H10D 30/801
FETs having rectifying junction gate electrodes: fETs having heterojunction gate electrodes
H10D 84/01
Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers:…