Combined digital-to-analog converter and latch memory circuit
AssigneeTektronix, Inc.
InventorEinar O. Traa
Life of this patent
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Abstract
A combined digital-to-analog converter and latch memory circuit (10) includes an R-2R resistive ladder network (12) and a current-controlled latch memory 18. The R-2R resistive ladder network has plural input nodes (100 and 102) and an analog signal output (104). Each of the input nodes corresponds to a different bit of a digital word that is to be converted to an analog signal. The current-controlled latch memory includes plural subcircuits (14 and 16). Each of the latch subcircuits uses an amount of current to store the logic state of the bit of the digital word and to derive directly the node of the R-2R resistive ladder network. This configuration promotes the efficient use of space, power, and circuit elements.
Claims4
A combined digital-to-analog converter and latch memory circuit, comprising:
- a resistive ladder network having plural input nodes and an output, each of the input nodes corresponding to a different bit of a digital word;
- plural current-controlled latch subcircuits, each of the latch subcircuits using an amount of current to control the operation thereof and having a current output for delivering the amount of current to one of the input nodes to represent the logic state of a corresponding one of the bits, thereby to store in the latch subcircuits the logic states of the bits of the digital word and to provide at the output an analog signal that corresponds to the weighted value of the digital word, said latch subscripts being mutually coupled in a series, and each having a data input and a data output, the data output of one of said latch subcircuits being coupled to the data input of the next adjacent latch subcircuit in the series to form a serial shift register;
- and
- positive and negative clock input terminals for receiving a differential clock signal such that said latch subcircuits are responsive to the clock signal in order to store data applied to their inputs.
Dependencies are inferred from the claim text.