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US 4,733,205 AGranted
Electrical filter
AssigneeU.S. Philips Corporation
InventorJohn B. Hughes
Life of this patent
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AssigneeU.S. Philips Corporation
InventorJohn B. Hughes
Estimating the term…
A continuous time electrical filter fabricated as an integrated circuit includes capacitors (CF,CN) and resistors (R1,R2). Since capacitors and resistors are difficult to integrate with accurately defined values, a trimming circuit is provided which operates switches (S1-SN) to select appropriate ones of the capacitors (CN) to accurately define the cut-off frequency of the filter. The trimming circuit comprises a capacitor (TC2) which is charged through a resistor TR1 during a first period and which is discharged in incremental steps by capacitor (TC1). The number of incremental steps is counted by a counter (11) and transferred to a register (13). The outputs (S1-SN) of the register (13) control the switches (S1-SN). Alternatively the values of the filter resistors may be adjusted, a convenient procedure being to short out selected portions of the resistors. More than one capacitor or resistor may be adjusted using a single counter and register. The trimming circuit also includes a switch (TS11) which connects the parasitic capacitance (CP1, CP2) of the capacitor (TC1) and an underlying conductive layer (22) and of a dummy resistor and the underlying layer (22) in parallel with the capacitor (TC1). The filter circuit is arranged so that the parasitic capacitance between the resistor (R1) and an underlying conductive layer and that between the capacitors (CF, CN) and the underlying conductive layer are connected in parallel with the fixed capacitor CF.
An integrated electrical filter comprising at least one capacitor, at least one resistor, and a trimming circuit for adjusting the product of the resistance of the resistor and the capacitance of the capacitor, characterised in that the trimming circuit comprises means for charging a further capacitor from a reference voltage source through a further resistor for a first period comprising 2.sup.N periods of a clock signal, where N is a first integer, means for removing the charge from the further capacitor in discrete increments during a second period comprising 2.sup.N +P periods of the clock signal, where P is a second integer, first connection means for connecting a stray capacitance formed between the further capacitor and an underlying conductive layer in parallel with the further capacitor for a third period which comprises the first P periods of the clock signal occurring during the second period, means for counting the number of increments required to remove the charge accumulated on the further capacitor during the first period, and means for adjusting the value of said at least one capacitor or said at least one resistor in dependence on the number of increments counted.
Dependencies are inferred from the claim text.